Features • High-performance, Low-power AVR® 8-bit Microcontroller • • • • • • • • – 130 Powerful Instructions - Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 8 MIPS Throughput at 8 MHz – On-chip 2-cycle Multiplier Nonvolatile Program and Data Memories Self-programming In-System Programmable Flash Memory – 16K Bytes with Optional Boot Block (256 - 2K Bytes) Endurance: 1,000 Write/Erase Cycles – Boot Section Allows Reprogramming of Program
(SCL) (SDA) Pin Configurations (SDA) (SCL) 2 ATmega163(L)
ATmega163(L) Description The ATmega163 is a low-power CMOS 8-bit microcontroller based on the AVR architecture. By executing powerful instructions in a single clock cycle, the ATmega163 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Block Diagram Figure 1. Block Diagram PA0 - PA7 PC0 - PC7 PORTA DRIVERS PORTC DRIVERS VCC GND DATA DIR. REG. PORTA DATA REGISTER PORTA DATA REGISTER PORTC DATA DIR. REG.
The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
ATmega163(L) Port D (PD7..PD0) Port D is an 8-bit bidirectional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers can sink 20 mA. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. Port D also serves the functions of various special features of the ATmega163 as listed on page 110. The Port D pins are tristated when a reset condition becomes active, even if the clock is not running. RESET Reset input.
Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an onchip oscillator, as shown in Figure 2. Either a quartz crystal or a ceramic resonator may be used. Figure 2. Oscillator Connections External Clock To drive the device from an external clock source, XTAL1 should be driven as shown in Figure 3. Figure 3.
ATmega163(L) Architectural Overview The fast-access register file concept contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This means that during one single clock cycle, one Arithmetic Logic Unit (ALU) operation is executed. Two operands are output from the register file, the operation is executed, and the result is stored back in the register file - in one clock cycle.
The AVR uses a Harvard architecture concept - with separate memories and buses for program and data. The program memory is executed with a two stage pipeline. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is in-system re-programmable Flash memory. With the jump and call instructions, the whole 8K word address space is directly accessed.
ATmega163(L) The General Purpose Register File Figure 7 shows the structure of the 32 general purpose working registers in the CPU. Figure 7. AVR CPU General Purpose Working Registers 7 0 Addr.
In the different addressing modes these address registers have functions as fixed displacement, automatic increment and decrement (see the descriptions for the different instructions). The ALU - Arithmetic Logic Unit The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, ALU operations between registers in the register file are executed.
ATmega163(L) The lower 1120 Data Memory locations address the Register file, the I/O Memory, and the internal data SRAM. The first 96 locations address the Register File + I/O Memory, and the next 1024 locations address the internal data SRAM. The five different addressing modes for the data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-Decrement, and Indirect with Post-Increment. In the register file, registers R26 to R31 feature the indirect addressing pointer registers.
I/O Direct Figure 12. I/O Direct Addressing Operand address is contained in 6 bits of the instruction word. n is the destination or source register address. Data Direct Figure 13. Direct Data Addressing Data Space 20 19 31 OP $0000 16 Rr/Rd 16 LSBs 15 0 $045F A 16-bit Data Address is contained in the 16 LSBs of a two-word instruction. Rd/Rr specify the destination or source register. Data Indirect With Displacement Figure 14.
ATmega163(L) Data Indirect Figure 15. Data Indirect Addressing Data Space $0000 15 0 X, Y OR Z - REGISTER $045F Operand address is the contents of the X, Y, or the Z-register. Data Indirect With Pre-decrement Figure 16. Data Indirect Addressing With Pre-decrement Data Space $0000 15 0 X, Y OR Z - REGISTER -1 $045F The X, Y or the Z-register is decremented before the operation. Operand address is the decremented contents of the X, Y or the Z-register. Data Indirect With Post-increment Figure 17.
Constant Addressing Using The LPM and SPM Instructions Figure 18. Code Memory Constant Addressing $1FFF Constant byte address is specified by the Z-register contents. The 15 MSBs select word address (0 - 8K). For LPM, the LSB selects low byte if cleared (LSB = 0) or high byte if set (LSB = 1). For SPM, the LSB should be cleared. Indirect Program Addressing, IJMP and ICALL Figure 19. Indirect Program Memory Addressing $1FFF Program execution continues at address contained by the Z-register (i.e.
ATmega163(L) The EEPROM Data Memory The ATmega163 contains 512 bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described on page 53 specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register. For the SPI data downloading, see page 132 for a detailed description.
Figure 23. On-chip Data SRAM Access Cycles T1 T2 T3 T4 System Clock Ø Address Prev. Address Address Write Data WR Read Data RD I/O Memory The I/O space definition of the ATmega163 is shown in the following table: Table 2.
ATmega163(L) Table 2.
Table 2. ATmega163 I/O Space (Continued) Note: I/O Address (SRAM Address) Name Function $04 ($24) ADCL ADC Data Register Low $03 ($23) TWDR 2-wire Serial Interface Data Register $02 ($22) TWAR 2-wire Serial Interface (Slave) Address Register $01 ($21) TWSR 2-wire Serial Interface Status Register $00 ($20) TWBR 2-wire Serial Interface Bit Rate Register Reserved and unused locations are not shown in the table. All ATmega163 I/Os and peripherals are placed in the I/O space.
ATmega163(L) • Bit 2 - N: Negative Flag The negative flag N indicates a negative result in an arithmetic or logic operation. See the Instruction Set Description for detailed information. • Bit 1 - Z: Zero Flag The zero flag Z indicates a zero result in an arithmetic or logic operation. See the Instruction Set Description for detailed information. • Bit 0 - C: Carry Flag The carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed information.
Table 3. Reset and Interrupt Vectors Vector No.
ATmega163(L) ; $024 ldi r16,high(RAMEND); Main program start $025 out SPH,r16 $026 ldi r16,low(RAMEND) $027 out SPL,r16 ... MAIN: ... ; Set stack pointer to top of RAM ... When the BOOTRST fuse is programmed and the boot section size set to 512 bytes, the most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega163 is: Address Labels $002 ... Code jmp ... $022 Comments EXT_INT0 ; IRQ0 Handler TWSI ; 2-wire Serial Interface Interrupt Handler ...
Figure 24. Reset Logic DATA BUS PORF BORF EXTRF WDRF MCU Status Register (MCUSR) Brown-Out Reset Circuit BODEN BODLEVEL 100-500kΩ SPIKE FILTER Clock Generator CK Delay Counters TIMEOUT CKSEL[3:0] Table 4. Reset Characteristics (VCC = 5.0V)(1) Symbol VPOT Parameter Condition Min Typ Max Units 1.0 1.4 1.8 V 0.4 0.6 0.8 V - - 0.85 VCC V (BODLEVEL = 1) 2.5 2.7 2.9 (BODLEVEL = 0) 3.6 4.0 4.
ATmega163(L) Table 5. Reset Delay Selections(1) (Continued) CKSEL(2) Start-up Time, VCC = 2.7V, BODLEVEL Unprogrammed Start-up Time, VCC = 4.0V, BODLEVEL Programmed 0111 30 µs + 6 CK(4) 10 µs + 6 CK(5) 1000 67ms + 32K CK 92 ms + 32K CK Ext. Low-frequency Crystal 1001 67 ms + 1K CK 92 ms + 1K CK Ext. Low-frequency Crystal 1010 67 ms + 16K CK 92 ms + 16K CK Crystal Oscillator, slowly rising power 1011 4.2 ms + 16K CK 5.
Figure 25. MCU Start-up, RESET Tied to VCC. VCC RESET VPOT VRST tTOUT TIME-OUT INTERNAL RESET Figure 26. MCU Start-up, RESET Extended Externally VCC VPOT RESET TIME-OUT VRST tTOUT INTERNAL RESET External Reset An external reset is generated by a low level on the RESET pin. Reset pulses longer than 500 ns will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.
ATmega163(L) Brown-out Detection ATmega163 has an on-chip brown-out detection (BOD) circuit for monitoring the VCC level during the operation. The BOD circuit can be enabled/disabled by the fuse BODEN. When the BOD is enabled (BODEN programmed), and VCC decreases to a value below the trigger level, the brown-out reset is immediately activated. When VCC increases above the trigger level, the brown-out reset is deactivated after a delay.
MCU Status Register - MCUSR The MCU Status Register provides information on which reset source caused an MCU reset. Bit 7 6 5 4 3 2 1 0 $34 ($54) - - - - WDRF BORF EXTRF PORF Read/Write R R R R R/W R/W R/W R/W Initial value 0 0 0 0 MCUSR See bit description • Bits 7..4 - Res: Reserved Bits These bits are reserved bits in the ATmega163 and always read as zero. • Bit 3 - WDRF: Watchdog Reset Flag This bit is set if a watchdog reset occurs.
ATmega163(L) Note that external level interrupt does not have a flag, and will only be remembered for as long as the interrupt condition is present. Note that the status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by software. Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is 4 clock cycles minimum.
• Bit 6 - INTF0: External Interrupt Flag0 When an event on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the interrupt vector at address $002. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared when INT0 is configured as a level interrupt. • Bits 5..
ATmega163(L) The Timer/Counter Interrupt Flag Register - TIFR Bit 7 6 5 4 3 2 1 0 OCF2 TOV2 ICF1 OCF1A OCF1B TOV1 - TOV0 Read/Write R/W R/W R/W R/W R/W R/W R R/W Initial value 0 0 0 0 0 0 x 0 $38 ($58) TIFR • Bit 7 - OCF2: Output Compare Flag 2 The OCF2 bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCR2 - Output Compare Register2. OCF2 is cleared by hardware when executing the corresponding interrupt handling vector.
MCU Control Register - MCUCR The MCU Control Register contains control bits for general MCU functions. Bit 7 6 5 4 3 2 1 0 $35 ($55) - SE SM1 SM0 ISC11 ISC10 ISC01 ISC00 Read/Write R R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 MCUCR • Bit 7 - Res: Reserved Bit This bit is a reserved bit in the ATmega163 and always reads as zero.
ATmega163(L) Table 9. Interrupt 0 Sense Control ISC01 ISC00 Description 0 0 The low level of INT0 generates an interrupt request. 0 1 Any logical change on INT0 generates an interrupt request. 1 0 The falling edge of INT0 generates an interrupt request. 1 1 The rising edge of INT0 generates an interrupt request. Sleep Modes To enter any of the four sleep modes, the SE bit in MCUCR must be set (one) and a SLEEP instruction must be executed.
When waking up from Power-down Mode, there is a delay from the wake-up condition occurs until the wake-up becomes effective. This allows the clock to restart and become stable after having been stopped. The wake-up period is defined by the same CKSEL fuses that define the reset time-out period, as seen in Table 5 on page 22. Power Save Mode When the SM1/SM0 bits are 11, the SLEEP instruction forces the MCU into the Power Save Mode.
ATmega163(L) • Bit 3 - ACME: Analog Comparator Multiplexer Enable When this bit is set (one) and the ADC is switched off (ADEN in ADCSR is zero), the ADC multiplexer selects the negative input to the Analog Comparator. When this bit is cleared (zero), AIN1 is applied to the negative input of the Analog Comparator. For a detailed description of this bit, see “Analog Comparator Multiplexed Input” on page 89. • Bit 2 - PUD: Pull-up Disable When this bit is set (one), all pull-ups on all ports are disabled.
sources. Setting the PSR10 bit in SFIOR resets the prescaler. This allows the user to operate with a predictable prescaler. Note that Timer/Counter1 and Timer/Counter 0 share the same prescaler and a prescaler reset will affect both Timer/Counters. Figure 31. Prescaler for Timer/Counter2 PCK2 PSR2 PCK2/1024 PCK2/256 PCK2/128 AS2 PCK2/64 10-BIT T/C PRESCALER Clear PCK2/32 TOSC1 PCK2/8 CK 0 CS20 CS21 CS22 TIMER/COUNTER2 CLOCK SOURCE TCK2 The clock source for Timer/Counter2 is named PCK2.
ATmega163(L) Figure 32. Timer/Counter0 Block Diagram TOIE0 7 CS00 CS01 CS02 T/C0 CONTROL REGISTER (TCCR0) TOV0 TOV1 OCF1A ICF1 OCF1B TIMER INT. FLAG REGISTER (TIFR) OCF2 TIMER INT.
Timer/Counter 0 - TCNT0 Bit 7 6 5 4 3 2 1 0 $34 ($54) MSB LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 TCNT0 The Timer/Counter0 is implemented as an up-counter with read and write access. If the Timer/Counter0 is written and a clock source is present, the Timer/Counter0 continues counting in the clock cycle following the write operation. 16-bit Timer/Counter1 Figure 33 shows the block diagram for Timer/Counter1. Figure 33.
ATmega163(L) The 16-bit Timer/Counter1 features both a high resolution and a high accuracy usage with the lower prescaling opportunities. Similarly, the high prescaling opportunities makes the Timer/Counter1 useful for lower speed functions or exact timing functions with infrequent actions. The Timer/Counter1 supports two Output Compare functions using the Output Compare Register 1 A and B (OCR1A and OCR1B) as the data sources to be compared to the Timer/Counter1 contents.
In PWM mode, these bits have a different function. Refer to Table 14 for a detailed description. • Bit 3 - FOC1A: Force Output Compare1A Writing a logical one to this bit, forces a change in the compare match output pin PD5 according to the values already set in COM1A1 and COM1A0. If the COM1A1 and COM1A0 bits are written in the same cycle as FOC1A, the new settings will not take effect until next compare match or forced compare match occurs.
ATmega163(L) ... | C-1, C-1, C-1, C-1, C-1, C-1, C-1, C-1 | C, C, C, C, C, C, C, C | 0, 0, 0, 0, 0, 0, 0, 0 |1,1,1,1,1,1,1,1|... In PWM mode, this bit has a different function. If the CTC1 bit is cleared in PWM mode, the Timer/Counter1 acts as an up/down counter. If the CTC1 bit is set (one), the Timer/Counter wraps when it reaches the TOP value. Refer to page 41 for a detailed description. • Bits 2..
The Timer/Counter1 is realized as an up or up/down (in PWM mode) counter with read and write access. If Timer/Counter1 is written to and a clock source is selected, the Timer/Counter1 continues counting in the timer clock cycle after it is preset with the written value.
ATmega163(L) Since the Input Capture Register - ICR1 - is a 16-bit register, a temporary register TEMP is used when ICR1 is read to ensure that both bytes are read simultaneously. When the CPU reads the low byte ICR1L, the data is sent to the CPU and the data of the high byte ICR1H is placed in the TEMP register. When the CPU reads the data in the high byte ICR1H, the CPU receives the data in the TEMP register.
Table 17. Compare1 Mode Select in PWM Mode CTC1 COM1X 1 COM1X 0 0 0 0 Not connected 0 0 1 Not connected 0 1 0 Cleared on compare match, up-counting. Set on compare match, down-counting (non-inverted PWM). 0 1 1 Cleared on compare match, down-counting. Set on compare match, up-counting (inverted PWM). 1 0 0 Not connected 1 0 1 Not connected 1 1 0 Cleared on compare match, set on overflow. 1 X = A or B 1 Set on compare match, cleared on overflow.
ATmega163(L) Figure 36. Effects of Unsynchronized OCR1 Latching in Overflow Mode. PWM Output OC1x Synchronized OC1x Latch PWM Output OC1x Unsynchronized OC1x Latch Note: X = A or B During the time between the write and the latch operation, a read from OCR1A or OCR1B will read the contents of the temporary location. This means that the most recently written value always will read out of OCR1A/B.
8-Bit Timer/Counter 2 Figure 37 shows the block diagram for Timer/Counter2. Figure 37. Timer/Counter2 Block Diagram T/C2 OVER- T/C2 COMPARE FLOW IRQ MATCH IRQ 8-BIT DATA BUS 0 TIMER/COUNTER2 (TCNT2) CS20 CS21 CS22 CTC2 COM20 COM21 FOC2 TOV0 TOV1 OCF1B ICF1 OCF1A T/C CLEAR T/C CLK SOURCE UP/DOWN 7 T/C2 CONTROL REGISTER (TCCR2) PWM2 OCF2 7 TOV2 TIMER INT. FLAG REGISTER (TIFR) OCF2 TIMER INT.
ATmega163(L) Timer/Counter2 Control Register - TCCR2 Bit 7 6 5 4 3 2 1 0 FOC2 PWM2 COM21 COM20 CTC2 CS22 CS21 CS20 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 $25 ($45) TCCR2 • Bit 7 - FOC2: Force Output Compare Writing a logical one to this bit, forces a change in the compare match output pin PD7 (OC2) according to the values already set in COM21 and COM20.
Table 20. Timer/Counter2 Prescale Select (Continued) CS22 CS21 CS20 Description 1 0 0 PCK2 / 64 1 0 1 PCK2 / 128 1 1 0 PCK2 / 256 1 1 1 PCK2 / 1024 The Stop condition provides a Timer Enable/Disable function. The prescaled modes are scaled directly from the PCK2 clock.
ATmega163(L) If CTC2 is set and PWM mode is selected, the Timer/Counters will wrap and start counting from $00 after reaching $FF. The PD7(OC2) pin will be set or cleared according to the settings of COM21/COM20 on a Timer/Counter overflow or when the counter value matches the contents of the Output Compare Register. Refer to Table 21 for details. Table 21.
Figure 39. Effects of Unsynchronized OCR Latching in Overflow Mode. Compare Value changes Counter Value Compare Value PWM Output OC2 Synchronized OC2 Latch Compare Value changes Counter Value Compare Value PWM Output OC2 Unsynchronized OC2 Latch Glitch During the time between the write and the latch operation, a read from OCR2 will read the contents of the temporary location. This means that the most recently written value always will read out of OCR2.
ATmega163(L) • Bit 2 - TCN2UB: Timer/Counter2 Update Busy When Timer/Counter2 operates asynchronously and TCNT2 is written, this bit becomes set (one). When TCNT2 has been updated from the temporary storage register, this bit is cleared (zero) by hardware. A logical zero in this bit indicates that TCNT2 is ready to be updated with a new value. • Bit 1 - OCR2UB: Output Compare Register2 Update Busy When Timer/Counter2 operates asynchronously and OCR2 is written, this bit becomes set (one).
• When the asynchronous operation is selected, the 32.768 kHZ oscillator for Timer/Counter2 is always running, except in power down mode. After a power-up reset or wake-up from power down, the user should be aware of the fact that this oscillator might take as long as one second to stabilize. The user is advised to wait for at least one second before using Timer/Counter2 after power-up or wake-up from power down.
ATmega163(L) Watchdog Timer The Watchdog Timer is clocked from a separate on-chip oscillator which runs at 1 Mhz. This is the typical value at VCC = 5V. See characterization data for typical values at other V CC levels. By controlling the Watchdog Timer prescaler, the Watchdog reset interval can be adjusted as shown in Table 23 on page 52. The WDR - Watchdog Reset - instruction resets the Watchdog Timer. Eight different clock cycle periods can be selected to determine the reset period.
• Bits 2..0 - WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1, and 0 The WDP2, WDP1, and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled. The different prescaling values and their corresponding Timeout Periods are shown in Table 23. Table 23. Watch Dog Timer Prescale Select 52 WDP2 WDP1 WDP0 Number of WDT Oscillator Cycles Typical Time-out at VCC = 3.0V Typical Time-out at VCC = 5.
ATmega163(L) EEPROM Read/Write Access The EEPROM access registers are accessible in the I/O space. The write access time is in the range of 1.9 - 3.8 ms, depending on the VCC voltages. See Table 24 for details. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains code that writes the EEPROM, some precautions must be taken. In heavily filtered power supplies, VCC is likely to rise or fall slowly on power-up/down.
• Bit 3 - EERIE: EEPROM Ready Interrupt Enable When the I bit in SREG and EERIE are set (one), the EEPROM Ready Interrupt is enabled. When cleared (zero), the interrupt is disabled. The EEPROM Ready interrupt generates a constant interrupt when EEWE is cleared (zero). • Bit 2 - EEMWE: EEPROM Master Write Enable The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written.
ATmega163(L) 1. Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal Brown-Out Detector (BOD) if the operating voltage matches the detection level. If not, an external low VCC Reset Protection circuit can be used. If a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply is voltage is sufficient. 2.
Serial Peripheral Interface - SPI The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega163 and peripheral devices or between several AVR devices.
ATmega163(L) Figure 42. SPI Master-slave Interconnection The system is single buffered in the transmit direction and double buffered in the receive direction. This means that bytes to be transmitted cannot be written to the SPI Data Register before the entire shift cycle is completed. When receiving data, however, a received character must be read from the SPI Data Register before the next character has been completely shifted in. Otherwise, the first byte is lost.
Data Modes There are four combinations of SCK phase and polarity with respect to serial data, which are determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Figure 43 and Figure 44. Figure 43. SPI Transfer Format with CPHA = 0 and DORD = 0 Figure 44.
ATmega163(L) • Bit 2 - CPHA: Clock Phase Refer to Figure 43 and Figure 44 for the functionality of this bit. • Bits 1,0 - SPR1, SPR0: SPI Clock Rate Select 1 and 0 These two bits control the SCK rate of the device configured as a master. SPR1 and SPR0 have no effect on the slave. The relationship between SCK and the Oscillator Clock frequency fck is shown in the following table: Table 26.
UART The ATmega163 features a full duplex (separate receive and transmit registers) Universal Asynchronous Receiver and Transmitter (UART).
ATmega163(L) • A new character has been written to UDR after the stop bit from the previous character has been shifted out. The shift register is loaded immediately. • A new character has been written to UDR before the stop bit from the previous character has been shifted out. The shift register is loaded when the stop bit of the character currently being transmitted has been shifted out.
samples 8, 9, and 10. If two or more of these three samples are found to be logical ones, the start bit is rejected as a noise spike and the receiver starts looking for the next 1 to 0-transition. If however, a valid start bit is detected, sampling of the data bits following the start bit is performed. These bits are also sampled at samples 8, 9, and 10. The logical value found in at least two of the three samples is taken as the bit value.
ATmega163(L) 1. All slave MCUs are in Multi-Processor Communication Mode (MPCM in UCSRA is set). 2. The master MCU sends an address byte, and all slaves receive and read this byte. In the slave MCUs, the RXC flag in UCSRA will be set as normal. 3. Each slave MCU reads the UDR register and determines if it has been selected. If so, it clears the MPCM bit in UCSRA, otherwise it waits for the next address byte. 4. For each received data byte, the receiving MCU will set the receive complete flag (RXC in UCSRA).
The FE bit is cleared when the stop bit of received data is one. • Bit 3 - OR: OverRun This bit is set if an Overrun condition is detected, i.e. when a character already present in the UDR register is not read before the next character has been shifted into the Receiver Shift register. The OR bit is buffered, which means that it will be set once the valid data still in UDR is read. The OR bit is cleared (zero) when data is received and transferred to UDR.
ATmega163(L) Baud Rate Generator The baud rate generator is a frequency divider which generates baud-rates according to the following equation: f CK BAUD = --------------------------------16(UBR + 1 ) • BAUD = Baud-Rate • fCK= Crystal Clock frequency • UBR = Contents of the UBRRHI and UBRR registers, (0-4095) • Note that this equation is not valid when the UART transmission speed is doubled. See “Double Speed Transmission” on page 66 for a detailed description.
UART Baud Rate Registers - UBRR and UBRRHI Bit 15 14 13 12 11 $20 ($40) - - - - MSB $09 ($29) MSB 7 Read/Write Initial value 6 5 4 3 10 9 2 8 LSB UBRRHI LSB UBRR 1 0 R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 This is a 12-bit register which contains the UART Baud Rate according to the equation on the previous page.
ATmega163(L) Table 28. UBR Settings at Various Crystal Frequencies in Double Speed Mode 1.0000 MHz % Error UBR = 51 1.8432 MHz 0.2 UBR = 95 % Error 2.0000 MHz % Error 0.0 UBR = 103 0.2 UBR = 25 0.2 UBR = 47 0.0 UBR = 51 0.2 UBR = 12 0.2 UBR = 23 0.0 UBR = 25 0.2 UBR = 8 3.7 UBR = 15 0.0 UBR = 16 2.1 UBR = 6 7.5 UBR = 11 0.0 UBR = 12 0.2 UBR = 3 7.8 UBR = 7 0.0 UBR = 8 3.7 UBR = 2 7.8 UBR = 5 0.0 UBR = 6 7.5 UBR = 1 7.8 UBR = 3 0.0 UBR = 3 7.8 UBR = 1 22.9 UBR = 2 0.
2-wire Serial Interface (Byte Oriented) The 2-wire Serial Interface supports bi-directional serial communication. It is designed primarily for simple but efficient integrated circuit (IC) control. The system is comprised of two lines, SCL (Serial Clock) and SDA (Serial Data) that carry information between the ICs connected to them. Various communication configurations can be designed using this bus. Figure 49 shows a typical 2-wire Serial Bus configuration.
ATmega163(L) Figure 51.
Note: Both the receiver and the transmitter can stretch the low period of the SCL line when waiting for user response, thereby reducing the average bit rate. TWBR should be set to a value higher than 7 to ensure correct 2-wire Serial Bus functionality. The bus alignment adjustion is automatically inserted by the 2-wire Serial Interface, and ensures the validity of setup and hold times on the bus for any TWBR value higher than 7.
ATmega163(L) The TWCR is used to control the operation of the 2-wire Serial Interface. It is used to enable the 2-wire Serial Interface, to initiate a master access by applying a START condition to the bus, to generate a receiver acknowledge, to generate a stop condition, and to control halting of the bus while the data to be written to the bus are written to the TWDR. It also indicates a write collision if data is attempted written to TWDR while the register is inaccessible.
ator that looks for the slave address (or generall call address if enabled) in the received serial address. If a match is found, an interrupt request is generated. 2-wire Serial Interface Modes The 2-wire Serial Interface can operate in four different modes: • Master Transmitter • Master Receiver • Slave Receiver • Slave Transmitter Data transfer in each mode of operation is shown in Figure 52 to Figure 55.
ATmega163(L) TWCR register. This scheme is repeated until the last byte is sent and the transfer is ended by generating a STOP condition or a repeated START condition. A STOP condition is generated by setting TWSTO, a repeated START condition is generated by setting TWSTA and TWSTO. After a repeated START condition (state $10) the 2-wire Serial Interface can access the same slave again, or a new slave without transmitting a STOP condition.
address by using the 2-wire Serial Bus clock as a clock source. The part will then wake up from sleep and the 2-wire Serial Interface will hold the SCL clock wil low during the wake up and until the TWINT flag is cleared. Note that the 2-wire Serial Interface Data Register - TWDR does not reflect the last byte present on the bus when waking up from these Sleep Modes. Assembly code illustrating operation of the slave receiver mode is given at the end of the TWI section.
ATmega163(L) Table 32.
Figure 52.
ATmega163(L) wait2: wait3: rjmp wait1 in r16, TWSR ; Check value of TWI Status Register. cpi r16, START ; If status different from START go to ERROR brne ERROR ldi r16, 0xc8 out TWDR, r16 ; Load SLA+W into TWDR register ldi r16, (1<
Table 33.
ATmega163(L) Figure 53.
wait6: in r16,TWCR ; Wait for TWINT flag set. This indicates that sbrs r16, TWINT ; SLA+R has been transmitted, and ACK/NACK has rjmp wait6 ; been received in r16, TWSR ; Check value of TWI Status Register. If status cpi r16, MR_SLA_ACK ; different from MR_SLA_ACK, go to ERROR brne ERROR ldi r16, (1<
ATmega163(L) brne ERROR in r16, TWDR ; Input received data from TWDR. nop ; ldi r16, (1<
Table 34.
ATmega163(L) Assembly Code Example - Slave Receiver Mode ;Part specific include file and TWI include file must be included. ; ldi r16, (1< wait10:in r16,TWCR ; Wait for TWINT flag set. This indicates that sbrs r16, TWINT ; START followed by SLA+W has been received rjmp wait10 in r16, TWSR ; Check value of TWI Status Register.
in r16, TWSR ; Check value of TWI Status Register. If status cpi r16, SR_DATA_NACK ; different from SR_DATA_NACK, go to ERROR brne ERROR in r16, TWDR ; Input received data from TWDR. nop ; ldi r16, (1<
ATmega163(L) Figure 55. Formats and States in the Slave Transmitter Mode Reception of the own slave address and one or more data bytes S SLA R A DATA $A8 Arbitration lost as master and addressed as slave A DATA $B8 A P or S $C0 A $B0 Last data byte transmitted.
in r16, TWSR ; Check value of TWI Status Register. If status cpi r16, ST_DATA_ACK ; different from ST_DATA_ACK, go to ERROR brne ERROR ldi r16, 0x44 out TWDR, r16 ldi r16, (1<
ATmega163(L) TWI Include File ;***** General Master staus codes ***** .equ START =$08 ;START has been transmitted .equ REP_START =$10 ;Repeated START has been transmitted ;***** Master Transmitter staus codes ***** .equ MT_SLA_ACK =$18 ;SLA+W has been tramsmitted and ACK received .equ MT_SLA_NACK =$20 ;SLA+W has been tramsmitted and NACK received .equ MT_DATA_ACK =$28 ;Data byte has been tramsmitted and ACK received .
The Analog Comparator The analog comparator compares the input values on the positive pin PB2 (AIN0) and negative pin PB3 (AIN1). When the voltage on the positive pin PB2 (AIN0) is higher than the voltage on the negative pin PB3 (AIN1), the Analog Comparator Output, ACO, is set (one). The comparator’s output can be set to trigger the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate interrupt, exclusive to the Analog Comparator.
ATmega163(L) • Bit 3 - ACIE: Analog Comparator Interrupt Enable When the ACIE bit is set (one) and the I-bit in the Status Register is set (one), the analog comparator interrupt is activated. When cleared (zero), the interrupt is disabled. • Bit 2 - ACIC: Analog Comparator Input Capture Enable When set (one), this bit enables the Input Capture function in Timer/Counter1 to be triggered by the analog comparator.
Analog to Digital Converter Feature List: • 10-bit Resolution • 0.5 LSB Integral Non-linearity • ±2 LSB Absolute Accuracy • 65 - 260 µs Conversion Time • Up to 15 kSPS at Maximum Resolution • Up to 76 kSPS at 8-bit Resolution • Eight Multiplexed Single Ended Input Channels • Optional Left Adjustment for ADC Result Readout • 0 - VCC ADC Input Voltage Range • Selectable 2.
ATmega163(L) Figure 57. Analog to Digital Converter Block Schematic ADC CONVERSION COMPLETE IRQ 0 ADC DATA REGISTER (ADCH/ADCL) ADC[9:0] ADPS0 ADPS2 ADPS1 ADIF ADFR ADEN ADSC MUX1 15 ADC CTRL. & STATUS REGISTER (ADCSR) MUX0 MUX2 MUX4 MUX3 REFS0 ADLAR REFS1 ADC MULTIPLEXER SELECT (ADMUX) ADIE ADIF 8-BIT DATA BUS PRESCALER CHANNEL SELECTION MUX DECODER AVCC CONVERSION LOGIC INTERNAL 2.56 V REFERENCE SAMPLE & HOLD COMPARATOR AREF 10-BIT DAC + AGND 1.
The ADC can operate in two modes - Single Conversion and Free Running Mode. In Single Conversion Mode, each conversion will have to be initiated by the user. In Free Running Mode, the ADC is constantly sampling and updating the ADC Data Register. The ADFR bit in ADCSR selects between the two available modes. The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSR. Voltage reference and input channel selections will not go into effect until ADEN is set.
ATmega163(L) switched on (ADEN in ADCSR is set). Additionally, when changing voltage reference, the user may improve accuracy by disregarding the first conversion result after the reference or MUX setting was changed. The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal conversion and 13.5 ADC clock cycles after the start of an extended conversion. When a conversion is complete, the result is written to the ADC data registers, and ADIF is set.
Figure 61. ADC Timing Diagram, Free Run Conversion One Conversion Cycle number 11 12 Next Conversion 13 1 2 3 4 ADC clock ADSC ADIF ADCH Sign and MSB of result ADCL LSB of result Sample & hold Conversion complete MUX and REFS update Table 39. ADC Conversion Time Sample & Hold (cycles from start of conversion) Conversion Time (cycles) Conversion Time (µs) Extended Conversion 13.5 25 125 - 500 Normal Conversions 1.
ATmega163(L) The ADC Multiplexer Selection Register - ADMUX Bit 7 6 5 4 3 2 1 0 REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 $07 ($27) ADMUX • Bit 7,6 - REFS1..0: Reference Selection Bits These bits select the voltage reference for the ADC, as shown in Table 17. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).
The ADC Control and Status Register - ADCSR Bit 7 6 5 4 3 2 1 0 ADEN ADSC ADFR ADIF ADIE ADPS2 ADPS1 ADPS0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 $06 ($26) ADCSR • Bit 7 - ADEN: ADC Enable Writing a logical ‘1’ to this bit enables the ADC. By clearing this bit to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion.
ATmega163(L) The ADC Data Register - ADCL and ADCH ADLAR = 0: Bit 15 14 13 12 11 10 9 8 $05 ($25) SIGN - - - - - ADC9 ADC8 ADCH $04 ($24) ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 ADCL 7 6 5 4 3 2 1 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/Write Initial value ADLAR = 1: Bit 15 14 13 12 11 10 9 8 $05 ($25) ADC9 ADC8 ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADCH $04 ($24) ADC1 ADC0 - - - - - - AD
PA3 (ADC3) 41 40 Analog Ground Plane PA2 (ADC2) 42 39 PA4 (ADC4) 38 PA5 (ADC5) 37 PA6 (ADC6) 36 PA7 (ADC7) 35 AREF 34 33 32 10µΗ PA1 (ADC1) 43 AGND 100nF PA0 (ADC0) 44 ATmega163 1 VCC GND Figure 62.
ATmega163(L) I/O-Ports All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies for changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input). Port A Port A is an 8-bit bi-directional I/O port with internal pull-ups.
Table 43. DDAn Effects on PORTA Pins DDAn PORTAn PUD I/O Pull Up Comment 0 0 x Input No Tri-state (Hi-Z) 0 1 1 Input No Tri-state (Hi-Z) 0 1 0 Input Yes PAn will source current if ext. pulled low. 1 0 x Output No Push-pull Zero Output 1 1 x Output No Push-pull One Output n: 7,6…0, pin number. PORT A Schematics Note that all port pins are synchronized. The synchronization latches are not shown in the figure. Figure 63.
ATmega163(L) The Port B pins with alternate functions are shown in Table 44. Table 44.
Table 45. DDBn Effects on Port B Pins DDBn PORTBn PUD I/O Pull Up Comment 0 0 x Input No Tri-state (Hi-Z) 0 1 1 Input No Tri-state (Hi-Z) 0 1 0 Input Yes PBn will source current if ext. pulled low. 1 0 x Output No Push-pull Zero Output 1 1 x Output No Push-pull One Output n: 7,6…0, pin number. Alternate Functions Of PORTB The alternate pin configuration is as follows: • SCK - PORTB, Bit 7 SCK: Master clock output, slave clock input pin for SPI channel.
ATmega163(L) Figure 64. PORTB Schematic Diagram (Pins PB0 and PB1) PUD PUD: PULL-UP DISABLE 2 Figure 65.
Figure 66. PORTB Schematic Diagram (Pin PB4) RD MOS PULLUP PUD RESET Q D DDB4 WD RESET Q D PORTB4 C PB4 RL DATA BUS C WP RP WP: WD: RL: RP: RD: MSTR: SPE: PUD: MSTR SPE WRITE PORTB WRITE DDRB READ PORTB LATCH READ PORTB PIN READ DDRB SPI MASTER ENABLE SPI ENABLE PULL-UP DISABLE SPI SS Figure 67.
ATmega163(L) Figure 68. PORTB Schematic Diagram (Pin PB6) RD MOS PULLUP PUD RESET R Q D DDB6 C DATA BUS WD RESET R Q D PORTB6 PB6 C RL WP RP WP: WD: RL: RP: RD: SPE: MSTR PUD: WRITE PORTB WRITE DDRB READ PORTB LATCH READ PORTB PIN READ DDRB SPI ENABLE MASTER SELECT PULL-UP DISABLE MSTR SPE SPI SLAVE OUT SPI MASTER IN Figure 69.
Port C Port C is an 8-bit bi-directional I/O port with internal pull-ups. Three I/O memory address locations are allocated for the Port C, one each for the Data Register - PORTC, $15($35), Data Direction Register - DDRC, $14($34) and the Port C Input Pins - PINC, $13($33). The Port C Input Pins address is read only, while the Data Register and the Data Direction Register are read/write. All port pins have individually selectable pull-up resistors.
ATmega163(L) Table 47. DDCn Effects on PORT C Pins DDCn PORTCn PUD I/O Pull Up Comment 0 0 x Input No Tri-state (Hi-Z) 0 1 1 Input No Tri-state (Hi-Z) 0 1 0 Input Yes PCn will source current if ext. pulled low.
Figure 70. PORTC Schematic Diagram (Pins PC0 - PC1) 0 DDCn PUD 1 PCn n 0 1 SCL/SDA out SCL/SDA in TWEN PUD: PULL-UP DISABLE n = 0, 1 Figure 71. PORTC Schematic Diagram (Pins PC2 - PC5) RD MOS PULLUP PUD RESET Q R D DDCn WD RESET R Q D PORTCn PCn C RL RP WP: WD: RL: RP: RD: PUD: n: 108 WRITE PORTC WRITE DDRC READ PORTC LATCH READ PORTC PIN READ DDRC PULL-UP DISABLE 2..
ATmega163(L) Figure 72. PORTC Schematic Diagram (Pins PC6) RD PUD MOS PULLUP RESET Q R D DDC6 WD RESET R Q D PORTC6 PC6 DATA BUS C C RL WP RP 0 1 AS2 T/C2 OSC AMP INPUT WP: WD: RL: RP: RD: AS2: PUD: WRITE PORTC WRITE DDRC READ PORTC LATCH READ PORTC PIN READ DDRC ASYNCH SELECT T/C2 PULL-UP DISABLE Figure 73.
Port D Port D is an 8 bit bi-directional I/O port with internal pull-up resistors. Three I/O memory address locations are allocated for Port D, one each for the Data Register - PORTD, $12($32), Data Direction Register - DDRD, $11($31) and the Port D Input Pins - PIND, $10($30). The Port D Input Pins address is read only, while the Data Register and the Data Direction Register are read/write. The Port D output buffers can sink 20 mA.
ATmega163(L) pin has to be configured as an output pin, or the PUD bit has to be set. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Table 49. DDDn Bits on Port D Pins DDDn PORTDn PUD I/O Pull Up Comment 0 0 x Input No Tri-state (Hi-Z) 0 1 1 Input No Tri-state (Hi-Z) 0 1 0 Input Yes PDn will source current if ext. pulled low.
Figure 74. PORTD Schematic Diagram (Pin PD0) RD MOS PULLUP PUD RESET Q D DDD0 C DATA BUS WD RESET Q D PORTD0 C PD0 RL WP RP WP: WD: RL: RP: RD: RXD: RXEN: PUD: RXEN WRITE PORTD WRITE DDRD READ PORTD LATCH READ PORTD PIN READ DDRD UART RECEIVE DATA UART RECEIVE ENABLE PULL-UP DISABLE RXD Figure 75.
ATmega163(L) Figure 76. PORTD Schematic Diagram (Pins PD2 and PD3) PUD PUD: PULL-UP DISABLE n: 2, 3 m: 0, 1 Figure 77.
Figure 78. PORTD Schematic Diagram (Pin PD6) RD MOS PULLUP PUD RESET Q R D DDD6 WD RESET R Q D PORTD6 PD6 DATA BUS C C RL WP RP WP: WD: RL: RP: RD: ACIC: ACO: PUD: WRITE PORTD WRITE DDRD READ PORTD LATCH READ PORTD PIN READ DDRD COMPARATOR IC ENABLE COMPARATOR OUTPUT PULL-UP DISABLE 0 NOISE CANCELER EDGE SELECT ICNC1 ICES1 ACIC ACO Figure 79.
ATmega163(L) Memory Programming Boot Loader Support The ATmega163 provides a mechanism for programming and reprogramming code by the MCU itself. This feature allows flexible application software updates, controlled by the MCU using a Flash-resident Boot Loader program. This makes it possible to program the AVR in a target system without access to its SPI pins.
Figure 80.
ATmega163(L) Table 51. Boot Reset Fuse BOOTRST Reset Address 0 Reset Vector = Application reset (address $0000) 1 Reset Vector = Boot Loader reset (see Table 50) Capabilities of the Boot Loader The program code within the Boot Loader section has the capability to read from and write into the entire Flash, including the Boot Loader Memory. This allows the user to update both the Application code and the Boot Loader code that handles the software update.
Wait for SPM Instruction to Complete Though the CPU is halted during page write, page erase or Lock bit write, for future compatibility, the user software must poll for SPM complete by reading the SPMCR register and loop until the SPMEN bit is cleared after a programming operation. See “Assembly code example for a Boot Loader” on page 121 for a code example.
ATmega163(L) Table 53. Boot Lock Bit1 Protection Modes (Boot Loader Section) BLB1 mode BLB12 BLB11 Protection 1 1 1 No restrictions for SPM, LPM accessing the Boot Loader section 2 1 0 SPM is not allowed to write to the Boot Loader section 3 0 0 SPM is not allowed to write to the Boot Loader section, and LPM executing from the Application section is not allowed to read from the Boot Loader section. If code is executed from Boot Section, the interrupts are disabled when BLB12 is programmed.
EEPROM Write Prevents Writing to SPMCR Note that an EEPROM write operation will block all software programming to Flash. Reading the Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It is recommended that the user checks the status bit (EEWE) in the EECR register and verifies that the bit is cleared before writing to the SPMCR register.
ATmega163(L) • Bit 2 - PGWRT: Page Write If this bit is set at the same time as SPMEN, the next SPM instruction within four clock cycles executes page write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a page write, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire page write operation.
ldi call spmcrval, (1<
ATmega163(L) rjmp ret Wait_spm Program And Data Memory Lock Bits The ATmega163 provides six Lock bits which can be left unprogrammed (‘1’) or can be programmed (‘0’) to obtain the additional features listed in Table 54. The Lock bits can only be erased to ‘1’ with the Chip Erase command. Table 54. Lock Bit Protection Modes Memory Lock Bits Protection Type LB mode LB1 LB2 1 1 1 No memory lock features enabled for parallel and serial programming.
• CKSEL3..0 select the clock source and the start-up delay after reset, according to Table 1 on page 5 and Table 5 on page 22. Default value is ‘0010’ (Internal RC Oscillator). The status of the Fuse bits is not affected by Chip Erase. Note that the Fuse bits are locked if lock bit1 (LB1) is programmed. Program the Fuse bits before programming the Lock bits. Signature Bytes All Atmel microcontrollers have a three-byte signature code which identifies the device.
ATmega163(L) Figure 81. Parallel Programming ATmega163 +5V RDY/BSY PD1 OE PD2 WR PD3 BS1 PD4 XA0 PD5 XA1 PD6 PAGEL PD7 VCC PB7 - PB0 +12 V DATA RESET BS2 PA0 XTAL1 GND Table 55.
Table 57. Command Byte Bit Coding Command Byte Command Executed 1000 0000 Chip Erase 0100 0000 Write Fuse Bits 0010 0000 Write Lock Bits 0001 0000 Write Flash 0001 0001 Write EEPROM 0000 1000 Read Signature Bytes 0000 0100 Read Fuse and Lock Bits 0000 0010 Read Flash 0000 0011 Read EEPROM Enter Programming Mode The following algorithm puts the device in parallel programming mode: 1. Apply 4.5 - 5.5V between VCC and GND. 2. Set RESET and BS pins to ‘0’ and wait at least 100 ns. 3.
ATmega163(L) 4. Give XTAL1 a positive pulse. This loads the address low byte. C. Load Data Low Byte 1. Set XA1, XA0 to ‘01’. This enables data loading. 2. Set DATA = Data low byte ($00 - $FF). 3. Give XTAL1 a positive pulse. This loads the data byte. D. Latch Data Low Byte 1. Set BS1 to ‘0’. This selects low data byte. 2. Give PAGEL a positive pulse. This latches the data low byte. (See Figure 82 for signal waveforms) E. Load Data High Byte 1. Set XA1, XA0 to ‘01’. This enables data loading. 2.
Figure 82. Programming the Flash Waveforms $10 DATA ADDR. LOW ADDR. HIGH DATA LOW XA1 XA2 BS1 XTAL1 WR RDY/BSY RESET +12V OE BS2 PAGEL Figure 83. Programming the Flash Waveforms (continued) DATA DATA HIGH XA1 XA0 BS1 XTAL1 WR RDY/BSY RESET +12V OE PAGEL BS2 Programming the EEPROM The programming algorithm for the EEPROM data memory is as follows (refer to “Programming the Flash” on page 126 for details on Command, Address and Data loading): 1. A: Load Command ‘0001 0001’. 2.
ATmega163(L) 3. Wait until to RDY/BSY goes high before programming the next byte. (See Figure 84 for signal waveforms) The loaded command and address are retained in the device during programming. For efficient programming, the following should be considered. • The command needs only be loaded once when writing or reading multiple memory locations. • Address high byte needs only be loaded before programming a new 256 word page in the EEPROM.
Programming the Fuse Low Bits The algorithm for programming the Fuse Low bits is as follows (refer to “Programming the Flash” on page 126 for details on Command and Data loading): 1. A: Load Command ‘0100 0000’. 2. C: Load Data Low Byte. Bit n = ‘0’ programs and bit n = ‘1’ erases the Fuse bit. Bit 7 = BODLEVEL Fuse bit Bit 6 = BODEN Fuse bit Bit 5 = SPIEN Fuse bit Bit 3..0 = CKSEL3..0 Fuse bits Bit 4 = ‘1’. This bit is reserved and should be left unprogrammed (‘1’). 3.
ATmega163(L) 3. Set OE to ‘0’, BS2 to ‘1’ and BS1 to ‘1’. The status of the Fuse High bits can now be read at DATA (‘0’ means programmed). Bit 2..1 = BOOTSZ1..0 Fuse bits Bit 0 = BOOTRST Fuse bit 4. Set OE to ‘0’, BS2 to ‘0’ and BS1 to ‘1’. The status of the Lock bits can now be read at DATA (‘0’ means programmed). Bit 5 = Boot Lock Bit12 Bit 4 = Boot Lock Bit11 Bit 3 = Boot Lock Bit02 Bit 2 = Boot Lock Bit01 Bit 1 = Lock Bit2 Bit 0 = Lock Bit1 5. Set OE to ‘1’.
Table 58. Parallel Programming Characteristics, TA = 25°C ± 10%, VCC = 5 V ± 10% Symbol Parameter Min VPP Programming Enable Voltage 11.
ATmega163(L) Figure 86. Serial Programming and Verify ATmega163 +5V VCC MOSI PB5 MISO PB6 SCK PB7 XTAL1 RESET GND When programming the EEPROM, an auto-erase cycle is built into the self-timed programming operation (in the serial mode ONLY) and there is no need to first execute the Chip Erase instruction. The Chip Erase operation turns the content of every memory location in both the Program and EEPROM arrays into $FF.
positive pulse and issue a new Programming Enable command. If the $53 is not seen within 32 attempts, there is no functional device connected. 4. If a chip erase is performed (must be done to erase the Flash), wait 2•tWD_FLASH after the instruction, give RESET a positive pulse, and start over from Step 2. See Table 59 for the tWD_FLASH figure. 5. The Flash is programmed one page at a time.
ATmega163(L) Table 59. Maximum Programming Times for Non-Volatile Memory Operation Symbol Chip Erase Flash Write EEPROM Write (2) Fuse/lock bit write Notes: Number of RC oscillator cycles Parallel / serial programming 2.7V 5.0V Self programming(1) tWD_CE 16K 32 ms 30 ms 17 ms tWD_FLASH 8K 16 ms 15 ms 8.5 ms tWD_EEPROM 2K 4 ms 3.8 ms 2.2 ms tWD_FUSE 1K 2 ms 1.9 ms 1.1 ms 1. Includes variation over voltage and temperature after RC oscillator has been calibrated to 1.0 MHz 2.
Table 60. Serial Programming Instruction Set (Continued) Instruction Read Signature Byte Write Fuse Bits Write Fuse High Bits Read Fuse Bits Read Fuse High Bits Read Calibration Byte Note: Instruction Format Operation Byte 1 Byte 2 Byte 3 Byte4 0011 0000 xxxx xxxx xxxx xxbb oooo oooo Read Signature Byte o at address b.
ATmega163(L) Table 61. Serial Programming Characteristics, TA = -40°C to 85°C, VCC = 2.7V - 5.5V (Unless otherwise noted) Symbol Parameter 1/tCLCL Oscillator Frequency (VCC = 2.7 - 5.5 V) tCLCL 1/tCLCL Oscillator Period (VCC = 2.7 - 5.5 V) Oscillator Frequency (VCC = 4.0 - 5.5 V) tCLCL Oscillator Period (VCC = 4.0 - 5.
Electrical Characteristics Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C *NOTICE: Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-1.0V to VCC+0.5V Voltage on RESET with respect to Ground......-1.0V to +13.0V Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
ATmega163(L) TA = -40°C to 85°C, VCC = 2.7V to 5.5V (unless otherwise noted) (Continued) Symbol Parameter Condition Min Typ Max Units Active 4 MHz, VCC = 3V (ATmega163L) 5.0 mA Active 8 MHz, VCC = 5V (ATmega163) 15.0 mA Idle 4 MHz, VCC = 3V (ATmega163L) 2.5 mA Idle 8 MHz, VCC = 5V (ATmega163) 8 mA Power Supply Current ICC Power Down Mode(5) WDT enabled, VCC = 3V 9 15.0 µA WDT disabled, VCC = 3V <1 4.
External Clock Drive Waveforms Figure 89. External Clock Drive Waveforms External Clock Drive Table 62. External Clock Drive VCC = 2.7V to 5.5V VCC = 4.0V to 5.5V Min Max Min Max Units 0 4 0 8 MHz Symbol Parameter 1/tCLCL Oscillator Frequency tCLCL Clock Period 250 125 ns tCHCX High Time 100 50 ns tCLCX Low Time 100 50 ns tCLCH Rise Time 1.6 0.5 µs tCHCL Fall Time 1.6 0.5 µs Table 63.
ATmega163(L) Table 64. 2-wire Serial Bus Requirements Symbol Parameter VIL VIH Max Units Input Low-voltage -0.5 0.3 VCC V Input High-voltage 0.7 VCC VCC + 0.5 V - V 0.4 V 250 ns 0 50(2) ns -10 10 µA - 10 pF 0 400 kHz fSCL ≤ 100 kHz 4.0 - µs fSCL > 100 kHz 0.6 - µs fSCL ≤ 100 kHz(6) 4.7 - µs (7) 1.3 - µs fSCL ≤ 100 kHz 4.0 - µs fSCL > 100 kHz 0.
Figure 90.
ATmega163(L) Typical Characteristics - Preliminary Data Analog comparator offset voltage is measured as absolute offset. Figure 91. Analog Comparator Offset Voltage vs, Common Mode Voltage (VCC = 5V) 18 16 TA = 25˚C Offset Voltage (mV) 14 12 TA = 85˚C 10 8 6 4 2 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Common Mode Voltage (V) Figure 92. Analog Comparator Offset Voltage vs. Common Mode Voltage (VCC = 2.7V) 10 TA = 25˚C Offset Voltage (mV) 8 6 TA = 85˚C 4 2 0 0 0.5 1 1.5 2 2.
Figure 93. Analog Comparator Input Leakage Current (VCC = 6V; TA = 25°C) 60 50 30 I ACLK (nA) 40 20 10 0 -10 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 VIN (V) Figure 94. Watchdog Oscillator Frequency vs. VCC 1600 TA = 25˚C 1400 TA = 85˚C F RC (KHz) 1200 1000 800 600 400 200 0 2 2.5 3 3.5 4 4.5 Vcc (V) Sink and source capabilities of I/O ports are measured on one pin at a time. 144 ATmega163(L) 5 5.
ATmega163(L) Figure 95. Pull-up Resistor Current vs. Input Voltage (VCC = 5V) 120 TA = 25˚C 100 TA = 85˚C I OP (µA) 80 60 40 20 0 0 0.5 1 1.5 2 2.5 VOP (V) 3 3.5 4 4.5 5 Figure 96. Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) 30 TA = 25˚C 25 TA = 85˚C 15 I OP (µA) 20 10 5 0 0 0.5 1 1.5 2 2.
Figure 97. I/O Pin Sink Current vs. Output Voltage (VCC = 5V) 70 TA = 25˚C 60 TA = 85˚C 50 30 I OL (mA) 40 20 10 0 0 0.5 1 1.5 2 2.5 3 VOL (V) Figure 98. I/O Pin Source Current vs. Output Voltage (VCC = 5V) 20 TA = 25˚C 18 16 TA = 85˚C 14 I OH (mA) 12 10 8 6 4 2 0 0 0.5 1 1.5 2 2.5 VOH (V) 146 ATmega163(L) 3 3.5 4 4.
ATmega163(L) Figure 99. I/O Pin Sink Current vs. Output Voltage (VCC = 2.7V) 25 TA = 25˚C 20 TA = 85˚C 10 I OL (mA) 15 5 0 0 0.5 1 1.5 2 VOL (V) Figure 100. I/O Pin Source Current vs. Output Voltage (VCC = 2.7V) 6 TA = 25˚C 5 TA = 85˚C 3 I OH (mA) 4 2 1 0 0 0.5 1 1.5 2 2.
Figure 101. I/O Pin Input Threshold vs. VCC (TA = 25°C) 2.5 Threshold Voltage (V) 2 1.5 1 0.5 0 2.7 4.0 5.0 Vcc Figure 102. I/O Pin Input Hysteresis vs. VCC (TA = 25°C) 0.18 0.16 Input hysteresis (V) 0.14 0.12 0.1 0.08 0.06 0.04 0.02 0 2.7 4.0 Vcc 148 ATmega163(L) 5.
ATmega163(L) Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page $3F ($5F) $3E ($5E) $3D ($5D) $3C ($5C) $3B ($5B) $3A ($5A) $39 ($59) $38 ($58) $37 ($57) $36 ($56) $35 ($55) $34 ($54) $33 ($53) $32 ($52) $31 ($51) $30 ($50) $2F ($4F) $2E ($4E) $2D ($4D) $2C ($4C) $2B ($4B) $2A ($4A) $29 ($49) $28 ($48) $27 ($47) $26 ($46) $25 ($45) $24 ($44) $23 ($43) $22 ($42) $21 ($41) $20 ($40) $1F ($3F) $1E ($3E) $1D ($3D) $1C ($3C) $1B ($3B) $1A ($3A) $19 ($39) $18 ($38) $17 (
Register Summary (Continued) Address $00 ($20) Notes: Name TWBR Bit 7 Bit 6 Bit 5 2-wire Serial Interface Bit Rate Register Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 69 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. Some of the status flags are cleared by writing a logical one to them.
ATmega163(L) Instruction Set Summary Mnemonics Operands Description Operation Flags Rd ← Rd + Rr Rd ← Rd + Rr + C Rdh:Rdl ← Rdh:Rdl + K Rd ← Rd - Rr Rd ← Rd - K Rd ← Rd - Rr - C Rd ← Rd - K - C Rdh:Rdl ← Rdh:Rdl - K Rd ←=Rd • Rr Rd ← Rd •=K Rd ← Rd v Rr Rd ←=Rd v K Rd ← Rd ⊕ Rr Rd ← $FF − Rd Rd ← $00 − Rd Rd ← Rd v K Rd ← Rd • ($FF - K) Rd ← Rd + 1 Rd ← Rd − 1 Rd ← Rd • Rd Rd ← Rd ⊕ Rd Rd ← $FF R1:R0 ← Rd x Rr R1:R0 ← Rd x Rr R1:R0 ← Rd x Rr R1:R0 ← (Rd x Rr) << 1 R1:R0 ← (Rd x Rr) << 1 R1:R0 ← (Rd x R
BRTC BRVS BRVC BRIE BRID Mnemonics k k k k k Branch if T Flag Cleared Branch if Overflow Flag is Set Branch if Overflow Flag is Cleared Branch if Interrupt Enabled Branch if Interrupt Disabled Operands DATA TRANSFER INSTRUCTIONS MOV Rd, Rr MOVW Rd, Rr LDI Rd, K LD Rd, X LD Rd, X+ LD Rd, - X LD Rd, Y LD Rd, Y+ LD Rd, - Y LDD Rd,Y+q LD Rd, Z LD Rd, Z+ LD Rd, -Z LDD Rd, Z+q LDS Rd, k ST X, Rr ST X+, Rr ST - X, Rr ST Y, Rr ST Y+, Rr ST - Y, Rr STD Y+q,Rr ST Z, Rr ST Z+, Rr ST -Z, Rr STD Z+q,Rr STS k, Rr LP
ATmega163(L) SEN CLN SEZ CLZ SEI CLI SES CLS SEV CLV SET CLT SEH CLH NOP SLEEP WDR Set Negative Flag Clear Negative Flag Set Zero Flag Clear Zero Flag Global Interrupt Enable Global Interrupt Disable Set Signed Test Flag Clear Signed Test Flag Set Twos Complement Overflow. Clear Twos Complement Overflow Set T in SREG Clear T in SREG Set Half Carry Flag in SREG Clear Half Carry Flag in SREG No Operation Sleep Watchdog Reset N←1 N←0 Z←1 Z←0 I←1 I=← 0 S←1 S←0 V←1 V←0 T←1 T←0 H←1 H←0 (see specific descr.
Ordering Information Speed (MHz) Power Supply 4 2.7 - 5.5V 8 4.0 - 5.5V Ordering Code Package ATmega163L-4AC ATmega163L-4PC 44A 40P6 Commercial (0°C to 70°C) ATmega163L-4AI ATmega163L-4PI 44A 40P6 Industrial (-40°C to 85°C) ATmega163-8AC ATmega163-8PC 44A 40P6 Commercial (0°C to 70°C) ATmega163-8AI ATmega163-8PI 44A 40P6 Industrial (-40°C to 85°C) Package Type 44A 44-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP) 40P6 40-lead, 0.
ATmega163(L) Packaging Information 44A, 44-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP) Dimensions in Millimeters and (Inches)* 40P6, 40-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) Dimensions in Inches and (Millimeters) JEDEC STANDARD MS-011 AC 2.07(52.6) 2.04(51.8) 12.21(0.478) SQ 11.75(0.458) PIN 1 ID PIN 1 0.45(0.018) 0.30(0.012) 0.80(0.031) BSC .566(14.4) .530(13.5) .090(2.29) MAX 1.900(48.26) REF .220(5.59) MAX 10.10(0.394) SQ 9.90(0.386) 0.20(.008) 0.09(.
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