User guide

83
ATmega162/V
2513E–AVR–09/03
External Interrupts The External Interrupts are triggered by the INT0, INT1, INT2 pin, or any of the
PCINT15..0 pins. Observe that, if enabled, the interrupts will trigger even if the INT2..0
or PCINT15..0 pins are configured as outputs. This feature provides a way of generating
a software interrupt. The External Interrupts can be triggered by a falling or rising edge
or a low level (INT2 is only an edge triggered interrupt). This is set up as indicated in the
specification for the MCU Control Register – MCUCR and Extended MCU Control Reg-
ister – EMCUCR. When the external interrupt is enabled and is configured as level
triggered (only INT0/INT1), the interrupt will trigger as long as the pin is held low. The
pin change interrupt PCI1 will trigger if any enabled PCINT15..8 pin toggles. Pin change
interrupts PCI0 will trigger if any enabled PCINT7..0 pin toggles. The PCMSK1 and
PCMSK0 Registers control which pins contribute to the pin change interrupts. Note that
recognition of falling or rising edge interrupts on INT0 and INT1 requires the presence of
an I/O clock, described in “Clock Systems and their Distribution” on page 33. Low level
interrupts on INT0/INT1, the edge interrupt on INT2, and Pin change interrupts on
PCINT15..0 are detected asynchronously. This implies that these interrupts can be used
for waking the part also from sleep modes other than Idle mode. The I/O clock is halted
in all sleep modes except Idle mode.
Note that if a level triggered interrupt is used for wake-up from Power-down mode, the
changed level must be held for some time to wake up the MCU. This makes the MCU
less sensitive to noise. The changed level is sampled twice by the Watchdog Oscillator
clock. The period of the Watchdog Oscillator is 1 µs (nominal) at 5.0V and 25°C. The
frequency of the Watchdog Oscillator is voltage dependent as shown in “Electrical Char-
acteristics” on page 263. The MCU will wake up if the input has the required level during
this sampling or if it is held until the end of the start-up time. The start-up time is defined
by the SUT Fuses as described in “System Clock and Clock Options” on page 33. If the
level is sampled twice by the Watchdog Oscillator clock but disappears before the end
of the start-up time, the MCU will still wake up, but no interrupt will be generated. The
required level must be held long enough for the MCU to complete the wake up to trigger
the level interrupt.
MCU Control Register –
MCUCR
The MCU Control Register contains control bits for interrupt sense control and general
MCU functions.
• Bit 3, 2 – ISC11, ISC10: Interrupt Sense Control 1 Bit 1 and Bit 0
The External Interrupt 1 is activated by the external pin INT1 if the SREG I-bit and the
corresponding interrupt mask in the GICR are set. The level and edges on the external
INT1 pin that activate the interrupt are defined in Table 43. The value on the INT1 pin is
sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last
longer than one clock period will generate an interrupt. Shorter pulses are not guaran-
teed to generate an interrupt. If low level interrupt is selected, the low level must be held
until the completion of the currently executing instruction to generate an interrupt.
Bit 76543210
SRE SRW10 SE SM1 ISC11 ISC10 ISC01 ISC00 MCUCR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000