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Table Of Contents

Features
Pin Configurations
- Disclaimer
Overview
- Block Diagram
- ATmega161 and ATmega162 Compatibility
  - ATmega161 Compatibility Mode
- Pin Descriptions
- About Code Examples
AVR CPU Core
- Introduction
- Architectural Overview
- ALU – Arithmetic Logic Unit
- Status Register
- General Purpose Register File
  - The X-register, Y-register, and Z-register
- Stack Pointer
- Instruction Execution Timing
- Reset and Interrupt Handling
  - Interrupt Response Time
AVR ATmega162 Memories
- In-System Reprogrammable Flash Program Memory
- SRAM Data Memory
  - Data Memory Access Times
- EEPROM Data Memory
- I/O Memory
- External Memory Interface
- XMEM Register Description
System Clock and Clock Options
- Clock Systems and their Distribution
- Clock Sources
- Default Clock Source
- Crystal Oscillator
- Low-frequency Crystal Oscillator
- Calibrated Internal RC Oscillator
  - Oscillator Calibration Register – OSCCAL
- External Clock
- Clock output buffer
- Timer/Counter Oscillator
- System Clock Prescaler
  - Clock Prescale Register – CLKPR
Power Management and Sleep Modes
- MCU Control Register – MCUCR
- MCU Control and Status Register – MCUCSR
- Extended MCU Control Register – EMCUCR
- Idle Mode
- Power-down Mode
- Power-save Mode
- Standby Mode
- Extended Standby Mode
- Minimizing Power Consumption
System Control and Reset
- Resetting the AVR
- Reset Sources
- Power-on Reset
- External Reset
- Brown-out Detection
- Watchdog Reset
- MCU Control and Status Register – MCUCSR
- Internal Voltage Reference
  - Voltage Reference Enable Signals and Start-up Time
- Watchdog Timer
  - Watchdog Timer Control Register – WDTCR
- Timed Sequences for Changing the Configuration of the Watchdog Timer
Interrupts
- Interrupt Vectors in ATmega162
  - Moving Interrupts Between Application and Boot Space
  - General Interrupt Control Register – GICR
I/O-Ports
- Introduction
- Ports as General Digital I/O
- Alternate Port Functions
- Register Description for I/O-Ports
External Interrupts
- MCU Control Register – MCUCR
- Extended MCU Control Register – EMCUCR
- General Interrupt Control Register – GICR
- General Interrupt Flag Register – GIFR
- Pin Change Mask Register 1 – PCMSK1
- Pin Change Mask Register 0 – PCMSK0
8-bit Timer/Counter0 with PWM
- Overview
  - Registers
  - Definitions
- Timer/Counter Clock Sources
- Counter Unit
- Output Compare Unit
- Compare Match Output Unit
  - Compare Output Mode and Waveform Generation
- Modes of Operation
- Timer/Counter Timing Diagrams
- 8-bit Timer/Counter Register Description
Timer/Counter0, Timer/Counter1, and Timer/Counter3 Prescalers
- Internal Clock Source
- Prescaler Reset
- External Clock Source
- Special Function IO Register – SFIOR
16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3)
- Restriction in ATmega161 Compatibility Mode
- Overview
- Accessing 16-bit Registers
  - Reusing the Temporary High Byte Register
- Timer/Counter Clock Sources
- Counter Unit
- Input Capture Unit
- Output Compare Units
- Compare Match Output Unit
  - Compare Output Mode and Waveform Generation
- Modes of Operation
- Timer/Counter Timing Diagrams
- 16-bit Timer/Counter Register Description
8-bit Timer/Counter2 with PWM and Asynchronous operation
- Overview
  - Registers
  - Definitions
- Timer/Counter Clock Sources
- Counter Unit
- Output Compare Unit
- Compare Match Output Unit
  - Compare Output Mode and Waveform Generation
- Modes of Operation
- Timer/Counter Timing Diagrams
- 8-bit Timer/Counter Register Description
- Asynchronous operation of the Timer/Counter
- Timer/Counter Prescaler
  - Special Function IO Register – SFIOR
Serial Peripheral Interface – SPI
- SS Pin Functionality
- Data Modes
USART
- Dual USART
  - AVR USART vs. AVR UART – Compatibility
- Clock Generation
- Frame Formats
  - Parity Bit Calculation
- USART Initialization
- Data Transmission – The USART Transmitter
- Data Reception – The USART Receiver
- Asynchronous Data Reception
- Multi-processor Communication Mode
  - Using MPCM
- Accessing UBRRH/ UCSRC Registers
  - Write Access
  - Read Access
- USART Register Description
- Examples of Baud Rate Setting
Analog Comparator
- Analog Comparator Control and Status Register – ACSR
JTAG Interface and On-chip Debug System
- Features
- Overview
- Test Access Port – TAP
- TAP Controller
- Using the Boundary- scan Chain
- Using the On-chip Debug system
- On-chip debug specific JTAG instructions
- On-chip Debug Related Register in I/O Memory
  - On-chip Debug Register – OCDR
- Using the JTAG Programming Capabilities
- Bibliography
IEEE 1149.1 (JTAG) Boundary-scan
- Features
- System Overview
- Data Registers
- Boundary-scan Specific JTAG Instructions
- Boundary-scan Chain
- ATmega162 Boundary- scan Order
- Boundary-scan Description Language Files
Boot Loader Support – Read-While-Write Self-programming
- Features
- Application and Boot Loader Flash Sections
  - Application Section
  - BLS – Boot Loader Section
- Read-While-Write and No Read-While-Write Flash Sections
  - RWW – Read-While-Write Section
  - NRWW – No Read-While-Write Section
- Boot Loader Lock Bits
- Entering the Boot Loader Program
  - Store Program Memory Control Register – SPMCR
- Addressing the Flash During Self- programming
- Self-programming the Flash
Memory Programming
- Program And Data Memory Lock Bits
- Fuse Bits
  - Latching of Fuses
- Signature Bytes
- Calibration Byte
- Parallel Programming Parameters, Pin Mapping, and Commands
  - Signal Names
- Parallel Programming
- Serial Downloading
- SPI Serial Programming Pin Mapping
- Programming via the JTAG Interface
Electrical Characteristics
- Absolute Maximum Ratings*
- DC Characteristics
- External Clock Drive Waveforms
- External Clock Drive
- SPI Timing Characteristics
- External Data Memory Timing
ATmega162 Typical Characteristics
- Active Supply Current
- Idle Supply Current
- Power-down Supply Current
- Power-save Supply Current
- Standby Supply Current
- Pin Pull-up
- Pin Driver Strength
- Pin Thresholds and Hysteresis
- BOD Thresholds and Analog Comparator Offset
- Internal Oscillator Speed
- Current Consumption of Peripheral Units
- Current Consumption in Reset and Reset Pulsewidth
Register Summary
Instruction Set Summary
Ordering Information
Packaging Information
- 44A
- 40P6
- 44M1
Erratas
- ATmega162, all rev.
Datasheet Change Log for ATmega162
- Changes from Rev. 2513D-04/03 to Rev. 2513E-09/03
- Changes from Rev. 2513C-09/02 to Rev. 2513D-04/03
- Changes from Rev. 2513B-09/02 to Rev. 2513C-09/02
- Changes from Rev. 2513A-05/02 to Rev. 2513B-09/02
Table of Contents

ATmega162/V

2513E–AVR–09/03

• TOSC1/XCK0/OC3A – Port D, Bit 4

TOSC1, Timer Oscillator pin 1: When the AS2 bit in ASSR is set (one) to enable asyn-

chronous clocking of Timer/Counter2, pin PD4 is disconnected from the port, and

becomes the input of the inverting Oscillator Amplifier. In this mode, a crystal Oscillator

is connected to this pin, and the pin can not be used as an I/O pin.

XCK0, USART0 External Clock: The Data Direction Register (DDD4) controls whether

the clock is output (DDD4 set (one)) or input (DDD4 cleared (zero)). The XCK0 pin is

active only when USART0 operates in Synchronous mode.

OC3A, Output Compare Match A output: The PD4 pin can serve as an external output

for the Timer/Counter1 Output Compare A. The pin has to be configured as an output

(DDD4 set (one)) to serve this function. The OC4A pin is also the output pin for the

PWM mode timer function.

• INT1/ICP3 – Port D, Bit 3

INT1, External Interrupt Source 1: The PD3 pin can serve as an external interrupt

source.

ICP3, Input Capture Pin: The PD3 pin can act as an Input Capture pin for

Timer/Counter3.

• INT0/XCK1 – Port D, Bit 2

INT0, External Interrupt Source 0: The PD2 pin can serve as an external interrupt

source.

XCK1, USART1 External Clock: The Data Direction Register (DDD2) controls whether

the clock is output (DDD2 set (one)) or input (DDD2 cleared (zero)). The XCK1 pin is

active only when USART1 operates in Synchronous mode.

• TXD0 – Port D, Bit 1

TXD0, Transmit Data (Data output pin for USART0). When the USART0 Transmitter is

enabled, this pin is configured as an output regardless of the value of DDD1.