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Table Of Contents

Features
Pin Configurations
- Disclaimer
Overview
- Block Diagram
- ATmega161 and ATmega162 Compatibility
  - ATmega161 Compatibility Mode
- Pin Descriptions
- About Code Examples
AVR CPU Core
- Introduction
- Architectural Overview
- ALU – Arithmetic Logic Unit
- Status Register
- General Purpose Register File
  - The X-register, Y-register, and Z-register
- Stack Pointer
- Instruction Execution Timing
- Reset and Interrupt Handling
  - Interrupt Response Time
AVR ATmega162 Memories
- In-System Reprogrammable Flash Program Memory
- SRAM Data Memory
  - Data Memory Access Times
- EEPROM Data Memory
- I/O Memory
- External Memory Interface
- XMEM Register Description
System Clock and Clock Options
- Clock Systems and their Distribution
- Clock Sources
- Default Clock Source
- Crystal Oscillator
- Low-frequency Crystal Oscillator
- Calibrated Internal RC Oscillator
  - Oscillator Calibration Register – OSCCAL
- External Clock
- Clock output buffer
- Timer/Counter Oscillator
- System Clock Prescaler
  - Clock Prescale Register – CLKPR
Power Management and Sleep Modes
- MCU Control Register – MCUCR
- MCU Control and Status Register – MCUCSR
- Extended MCU Control Register – EMCUCR
- Idle Mode
- Power-down Mode
- Power-save Mode
- Standby Mode
- Extended Standby Mode
- Minimizing Power Consumption
System Control and Reset
- Resetting the AVR
- Reset Sources
- Power-on Reset
- External Reset
- Brown-out Detection
- Watchdog Reset
- MCU Control and Status Register – MCUCSR
- Internal Voltage Reference
  - Voltage Reference Enable Signals and Start-up Time
- Watchdog Timer
  - Watchdog Timer Control Register – WDTCR
- Timed Sequences for Changing the Configuration of the Watchdog Timer
Interrupts
- Interrupt Vectors in ATmega162
  - Moving Interrupts Between Application and Boot Space
  - General Interrupt Control Register – GICR
I/O-Ports
- Introduction
- Ports as General Digital I/O
- Alternate Port Functions
- Register Description for I/O-Ports
External Interrupts
- MCU Control Register – MCUCR
- Extended MCU Control Register – EMCUCR
- General Interrupt Control Register – GICR
- General Interrupt Flag Register – GIFR
- Pin Change Mask Register 1 – PCMSK1
- Pin Change Mask Register 0 – PCMSK0
8-bit Timer/Counter0 with PWM
- Overview
  - Registers
  - Definitions
- Timer/Counter Clock Sources
- Counter Unit
- Output Compare Unit
- Compare Match Output Unit
  - Compare Output Mode and Waveform Generation
- Modes of Operation
- Timer/Counter Timing Diagrams
- 8-bit Timer/Counter Register Description
Timer/Counter0, Timer/Counter1, and Timer/Counter3 Prescalers
- Internal Clock Source
- Prescaler Reset
- External Clock Source
- Special Function IO Register – SFIOR
16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3)
- Restriction in ATmega161 Compatibility Mode
- Overview
- Accessing 16-bit Registers
  - Reusing the Temporary High Byte Register
- Timer/Counter Clock Sources
- Counter Unit
- Input Capture Unit
- Output Compare Units
- Compare Match Output Unit
  - Compare Output Mode and Waveform Generation
- Modes of Operation
- Timer/Counter Timing Diagrams
- 16-bit Timer/Counter Register Description
8-bit Timer/Counter2 with PWM and Asynchronous operation
- Overview
  - Registers
  - Definitions
- Timer/Counter Clock Sources
- Counter Unit
- Output Compare Unit
- Compare Match Output Unit
  - Compare Output Mode and Waveform Generation
- Modes of Operation
- Timer/Counter Timing Diagrams
- 8-bit Timer/Counter Register Description
- Asynchronous operation of the Timer/Counter
- Timer/Counter Prescaler
  - Special Function IO Register – SFIOR
Serial Peripheral Interface – SPI
- SS Pin Functionality
- Data Modes
USART
- Dual USART
  - AVR USART vs. AVR UART – Compatibility
- Clock Generation
- Frame Formats
  - Parity Bit Calculation
- USART Initialization
- Data Transmission – The USART Transmitter
- Data Reception – The USART Receiver
- Asynchronous Data Reception
- Multi-processor Communication Mode
  - Using MPCM
- Accessing UBRRH/ UCSRC Registers
  - Write Access
  - Read Access
- USART Register Description
- Examples of Baud Rate Setting
Analog Comparator
- Analog Comparator Control and Status Register – ACSR
JTAG Interface and On-chip Debug System
- Features
- Overview
- Test Access Port – TAP
- TAP Controller
- Using the Boundary- scan Chain
- Using the On-chip Debug system
- On-chip debug specific JTAG instructions
- On-chip Debug Related Register in I/O Memory
  - On-chip Debug Register – OCDR
- Using the JTAG Programming Capabilities
- Bibliography
IEEE 1149.1 (JTAG) Boundary-scan
- Features
- System Overview
- Data Registers
- Boundary-scan Specific JTAG Instructions
- Boundary-scan Chain
- ATmega162 Boundary- scan Order
- Boundary-scan Description Language Files
Boot Loader Support – Read-While-Write Self-programming
- Features
- Application and Boot Loader Flash Sections
  - Application Section
  - BLS – Boot Loader Section
- Read-While-Write and No Read-While-Write Flash Sections
  - RWW – Read-While-Write Section
  - NRWW – No Read-While-Write Section
- Boot Loader Lock Bits
- Entering the Boot Loader Program
  - Store Program Memory Control Register – SPMCR
- Addressing the Flash During Self- programming
- Self-programming the Flash
Memory Programming
- Program And Data Memory Lock Bits
- Fuse Bits
  - Latching of Fuses
- Signature Bytes
- Calibration Byte
- Parallel Programming Parameters, Pin Mapping, and Commands
  - Signal Names
- Parallel Programming
- Serial Downloading
- SPI Serial Programming Pin Mapping
- Programming via the JTAG Interface
Electrical Characteristics
- Absolute Maximum Ratings*
- DC Characteristics
- External Clock Drive Waveforms
- External Clock Drive
- SPI Timing Characteristics
- External Data Memory Timing
ATmega162 Typical Characteristics
- Active Supply Current
- Idle Supply Current
- Power-down Supply Current
- Power-save Supply Current
- Standby Supply Current
- Pin Pull-up
- Pin Driver Strength
- Pin Thresholds and Hysteresis
- BOD Thresholds and Analog Comparator Offset
- Internal Oscillator Speed
- Current Consumption of Peripheral Units
- Current Consumption in Reset and Reset Pulsewidth
Register Summary
Instruction Set Summary
Ordering Information
Packaging Information
- 44A
- 40P6
- 44M1
Erratas
- ATmega162, all rev.
Datasheet Change Log for ATmega162
- Changes from Rev. 2513D-04/03 to Rev. 2513E-09/03
- Changes from Rev. 2513C-09/02 to Rev. 2513D-04/03
- Changes from Rev. 2513B-09/02 to Rev. 2513C-09/02
- Changes from Rev. 2513A-05/02 to Rev. 2513B-09/02
Table of Contents

ATmega162/V

2513E–AVR–09/03

Ports as General Digital

I/O

The ports are bi-directional I/O ports with optional internal pull-ups. Figure 29 shows a

functional description of one I/O-port pin, here generically called Pxn.

Figure 29. General Digital I/O

(1)

Note: 1. WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk

I/O

SLEEP, and PUD are common to all ports.

Configuring the Pin Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in

“Register Description for I/O-Ports” on page 81, the DDxn bits are accessed at the

DDRx I/O address, the PORTxn bits at the PORTx I/O address, and the PINxn bits at

the PINx I/O address.

The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written

logic one, Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is config-

ured as an input pin.

If PORTxn is written logic one when the pin is configured as an input pin, the pull-up

resistor is activated. To switch the pull-up resistor off, PORTxn has to be written logic

zero or the pin has to be configured as an output pin. The port pins are tri-stated when a

reset condition becomes active, even if no clocks are running.

If PORTxn is written logic one when the pin is configured as an output pin, the port pin is

driven high (one). If PORTxn is written logic zero when the pin is configured as an out-

put pin, the port pin is driven low (zero).

When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn,

PORTxn} = 0b11), an intermediate state with either pull-up enabled ({DDxn, PORTxn} =

0b01) or output low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up

clk

RPx

RRx

WRx

RDx

WDx

PUD

SYNCHRONIZER

WDx: WRITE DDRx

WRx: WRITE PORTx

RRx: READ PORTx REGISTER

RPx: READ PORTx PIN

PUD: PULLUP DISABLE

clk

I/O

: I/O CLOCK

RDx: READ DDRx

RESET

CLR

PORTxn

CLR

DDxn

PINxn

DATA BUS

SLEEP

SLEEP: SLEEP CONTROL

Pxn

I/O