User guide

39
ATmega162/V
2513E–AVR–09/03
will be output also during Reset and the normal operation of PortB will be overridden
when the fuse is programmed. Any clock sources, including Internal RC Oscillator, can
be selected when PortB 0 serves as clock output.
If the system clock prescaler is used, it is the divided system clock that is output when
the CKOUT Fuse is programmed. See “System Clock Prescaler” on page 39. for a
description of the system clock prescaler.
Timer/Counter Oscillator For AVR microcontrollers with Timer/Counter Oscillator pins (TOSC1 and TOSC2), the
crystal is connected directly between the pins. The Oscillator provides internal capaci-
tors on TOSC1 and TOSC2, thereby removing the need for external capacitors. The
internal capacitors have a nominal value of 10 pF. The Oscillator is optimized for use
with a 32.768 kHz watch crystal. Applying an external clock source to TOSC1 is not
recommended.
System Clock Prescaler The ATmega162 system clock can be divided by setting the Clock Prescale Register –
CLKPR. This feature can be used to decrease power consumption when the require-
ment for processing power is low. This can be used with all clock source options, and it
will affect the clock frequency of the CPU and all synchronous peripherals. clk
I/O
, clk
CPU
,
and clk
FLASH
are divided by a factor as shown in Table 15. Note that the clock frequency
of clk
ASY
(asynchronously Timer/Counter) only will be scaled if the Timer/Counter is
clocked synchronously.
Clock Prescale Register –
CLKPR
• Bit 7 – CLKPCE: Clock Prescaler Change Enable
The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. CLK-
PCE is cleared by hardware four cycles after it is written or when CLKPS is written.
Setting the CLKPCE bit will disable interrupts, as explained in the CLKPS description
below.
• Bits 3..0 – CLKPS3..0: Clock Prescaler Select Bits 3 - 0
These bits define the division factor between the selected clock source and the internal
system clock. These bits can be written run-time to vary the clock frequency to suit the
application requirements. As the divider divides the master clock input to the MCU, the
speed of all synchronous peripherals is reduced when a division factor is used. The divi-
sion factors are given in Table 15.
To avoid unintentional changes of clock frequency, a special write procedure must be
followed to change the CLKPS bits:
1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits
in CLKPR to zero.
2. Within four cycles, write the desired value to CLKPS while writing a zero to
CLKPCE.
Caution: An interrupt between step 1 and step 2 will make the timed sequence fail. It is
recommended to have the Global Interrupt Flag cleared during these steps to avoid this
problem.
Bit 76543210
CLKPCE – – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 CLKPR
Read/Write R/W R R R R/W R/W R/W R/W
Initial Value 0 0 0 0 See Bit Description