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Table Of Contents

Features
Pin Configurations
- Disclaimer
Overview
- Block Diagram
- ATmega161 and ATmega162 Compatibility
  - ATmega161 Compatibility Mode
- Pin Descriptions
- About Code Examples
AVR CPU Core
- Introduction
- Architectural Overview
- ALU – Arithmetic Logic Unit
- Status Register
- General Purpose Register File
  - The X-register, Y-register, and Z-register
- Stack Pointer
- Instruction Execution Timing
- Reset and Interrupt Handling
  - Interrupt Response Time
AVR ATmega162 Memories
- In-System Reprogrammable Flash Program Memory
- SRAM Data Memory
  - Data Memory Access Times
- EEPROM Data Memory
- I/O Memory
- External Memory Interface
- XMEM Register Description
System Clock and Clock Options
- Clock Systems and their Distribution
- Clock Sources
- Default Clock Source
- Crystal Oscillator
- Low-frequency Crystal Oscillator
- Calibrated Internal RC Oscillator
  - Oscillator Calibration Register – OSCCAL
- External Clock
- Clock output buffer
- Timer/Counter Oscillator
- System Clock Prescaler
  - Clock Prescale Register – CLKPR
Power Management and Sleep Modes
- MCU Control Register – MCUCR
- MCU Control and Status Register – MCUCSR
- Extended MCU Control Register – EMCUCR
- Idle Mode
- Power-down Mode
- Power-save Mode
- Standby Mode
- Extended Standby Mode
- Minimizing Power Consumption
System Control and Reset
- Resetting the AVR
- Reset Sources
- Power-on Reset
- External Reset
- Brown-out Detection
- Watchdog Reset
- MCU Control and Status Register – MCUCSR
- Internal Voltage Reference
  - Voltage Reference Enable Signals and Start-up Time
- Watchdog Timer
  - Watchdog Timer Control Register – WDTCR
- Timed Sequences for Changing the Configuration of the Watchdog Timer
Interrupts
- Interrupt Vectors in ATmega162
  - Moving Interrupts Between Application and Boot Space
  - General Interrupt Control Register – GICR
I/O-Ports
- Introduction
- Ports as General Digital I/O
- Alternate Port Functions
- Register Description for I/O-Ports
External Interrupts
- MCU Control Register – MCUCR
- Extended MCU Control Register – EMCUCR
- General Interrupt Control Register – GICR
- General Interrupt Flag Register – GIFR
- Pin Change Mask Register 1 – PCMSK1
- Pin Change Mask Register 0 – PCMSK0
8-bit Timer/Counter0 with PWM
- Overview
  - Registers
  - Definitions
- Timer/Counter Clock Sources
- Counter Unit
- Output Compare Unit
- Compare Match Output Unit
  - Compare Output Mode and Waveform Generation
- Modes of Operation
- Timer/Counter Timing Diagrams
- 8-bit Timer/Counter Register Description
Timer/Counter0, Timer/Counter1, and Timer/Counter3 Prescalers
- Internal Clock Source
- Prescaler Reset
- External Clock Source
- Special Function IO Register – SFIOR
16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3)
- Restriction in ATmega161 Compatibility Mode
- Overview
- Accessing 16-bit Registers
  - Reusing the Temporary High Byte Register
- Timer/Counter Clock Sources
- Counter Unit
- Input Capture Unit
- Output Compare Units
- Compare Match Output Unit
  - Compare Output Mode and Waveform Generation
- Modes of Operation
- Timer/Counter Timing Diagrams
- 16-bit Timer/Counter Register Description
8-bit Timer/Counter2 with PWM and Asynchronous operation
- Overview
  - Registers
  - Definitions
- Timer/Counter Clock Sources
- Counter Unit
- Output Compare Unit
- Compare Match Output Unit
  - Compare Output Mode and Waveform Generation
- Modes of Operation
- Timer/Counter Timing Diagrams
- 8-bit Timer/Counter Register Description
- Asynchronous operation of the Timer/Counter
- Timer/Counter Prescaler
  - Special Function IO Register – SFIOR
Serial Peripheral Interface – SPI
- SS Pin Functionality
- Data Modes
USART
- Dual USART
  - AVR USART vs. AVR UART – Compatibility
- Clock Generation
- Frame Formats
  - Parity Bit Calculation
- USART Initialization
- Data Transmission – The USART Transmitter
- Data Reception – The USART Receiver
- Asynchronous Data Reception
- Multi-processor Communication Mode
  - Using MPCM
- Accessing UBRRH/ UCSRC Registers
  - Write Access
  - Read Access
- USART Register Description
- Examples of Baud Rate Setting
Analog Comparator
- Analog Comparator Control and Status Register – ACSR
JTAG Interface and On-chip Debug System
- Features
- Overview
- Test Access Port – TAP
- TAP Controller
- Using the Boundary- scan Chain
- Using the On-chip Debug system
- On-chip debug specific JTAG instructions
- On-chip Debug Related Register in I/O Memory
  - On-chip Debug Register – OCDR
- Using the JTAG Programming Capabilities
- Bibliography
IEEE 1149.1 (JTAG) Boundary-scan
- Features
- System Overview
- Data Registers
- Boundary-scan Specific JTAG Instructions
- Boundary-scan Chain
- ATmega162 Boundary- scan Order
- Boundary-scan Description Language Files
Boot Loader Support – Read-While-Write Self-programming
- Features
- Application and Boot Loader Flash Sections
  - Application Section
  - BLS – Boot Loader Section
- Read-While-Write and No Read-While-Write Flash Sections
  - RWW – Read-While-Write Section
  - NRWW – No Read-While-Write Section
- Boot Loader Lock Bits
- Entering the Boot Loader Program
  - Store Program Memory Control Register – SPMCR
- Addressing the Flash During Self- programming
- Self-programming the Flash
Memory Programming
- Program And Data Memory Lock Bits
- Fuse Bits
  - Latching of Fuses
- Signature Bytes
- Calibration Byte
- Parallel Programming Parameters, Pin Mapping, and Commands
  - Signal Names
- Parallel Programming
- Serial Downloading
- SPI Serial Programming Pin Mapping
- Programming via the JTAG Interface
Electrical Characteristics
- Absolute Maximum Ratings*
- DC Characteristics
- External Clock Drive Waveforms
- External Clock Drive
- SPI Timing Characteristics
- External Data Memory Timing
ATmega162 Typical Characteristics
- Active Supply Current
- Idle Supply Current
- Power-down Supply Current
- Power-save Supply Current
- Standby Supply Current
- Pin Pull-up
- Pin Driver Strength
- Pin Thresholds and Hysteresis
- BOD Thresholds and Analog Comparator Offset
- Internal Oscillator Speed
- Current Consumption of Peripheral Units
- Current Consumption in Reset and Reset Pulsewidth
Register Summary
Instruction Set Summary
Ordering Information
Packaging Information
- 44A
- 40P6
- 44M1
Erratas
- ATmega162, all rev.
Datasheet Change Log for ATmega162
- Changes from Rev. 2513D-04/03 to Rev. 2513E-09/03
- Changes from Rev. 2513C-09/02 to Rev. 2513D-04/03
- Changes from Rev. 2513B-09/02 to Rev. 2513C-09/02
- Changes from Rev. 2513A-05/02 to Rev. 2513B-09/02
Table of Contents

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ATmega162/V

2513E–AVR–09/03

(0x60) Reserved – – – – – – – –

0x3F (0x5F) SREG I T H S V N Z C 8

0x3E (0x5E) SPH SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 11

0x3D (0x5D) SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 11

0x3C

(2)

(0x5C)

(2)

UBRR1H URSEL1

UBRR1[11:8]

189

UCSR1C URSEL1 UMSEL1 UPM11 UPM10 USBS1 UCSZ11 UCSZ10 UCPOL1 188

0x3B (0x5B) GICR INT1 INT0 INT2 PCIE1 PCIE0

– IVSEL IVCE 60, 85

0x3A (0x5A) GIFR INTF1 INTF0 INTF2 PCIF1 PCIF0

– – –86

0x39 (0x59) TIMSK TOIE1 OCIE1A OCIE1B OCIE2 TICIE1 TOIE2 TOIE0 OCIE0 101, 133, 154

0x38 (0x58) TIFR TOV1 OCF1A OCF1B OCF2 ICF1 TOV2 TOV0 OCF0 102, 135, 155

0x37 (0x57) SPMCR SPMIE RWWSB

– RWWSRE BLBSET PGWRT PGERS SPMEN 220

0x36 (0x56) EMCUCR SM0 SRL2 SRL1 SRL0 SRW01 SRW00 SRW11 ISC2 28,42,84

0x35 (0x55) MCUCR SRE SRW10 SE SM1 ISC11 ISC10 ISC01 ISC00 28,41,83

0x34 (0x54) MCUCSR JTD

– SM2 JTRF WDRF BORF EXTRF PORF 41,50,206

0x33 (0x53) TCCR0 FOC0 WGM00 COM01 COM00 WGM01 CS02 CS01 CS00 99

0x32 (0x52) TCNT0 Timer/Counter0 (8 Bits) 101

0x31 (0x51)

OCR0 Timer/Counter0 Output Compare Register 101

0x30 (0x50) SFIOR TSM XMBK XMM2 XMM1 XMM0 PUD PSR2 PSR310 30,69,104,156

0x2F (0x4F) TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 FOC1A FOC1B WGM11 WGM10 127

0x2E (0x4E) TCCR1B ICNC1 ICES1

– WGM13 WGM12 CS12 CS11 CS10 130

0x2D (0x4D) TCNT1H Timer/Counter1 – Counter Register High Byte 132

0x2C (0x4C) TCNT1L Timer/Counter1 – Counter Register Low Byte 132

0x2B (0x4B) OCR1AH Timer/Counter1 – Output Compare Register A High Byte 132

0x2A (0x4A) OCR1AL Timer/Counter1 – Output Compare Register A Low Byte 132

0x29 (0x49) OCR1BH Timer/Counter1 – Output Compare Register B High Byte 132

0x28 (0x48) OCR1BL Timer/Counter1 – Output Compare Register B Low Byte 132

0x27 (0x47) TCCR2 FOC2 WGM20 COM21 COM20 WGM21 CS22 CS21 CS20 148

0x26 (0x46) ASSR

– – – – AS2 TCON2UB OCR2UB TCR2UB 152

0x25 (0x45) ICR1H Timer/Counter1 – Input Capture Register High Byte 133

0x24 (0x44) ICR1L Timer/Counter1 – Input Capture Register Low Byte 133

0x23 (0x43) TCNT2 Timer/Counter2 (8 Bits) 151

0x22 (0x42) OCR2 Timer/Counter2 Output Compare Register 151

0x21 (0x41) WDTCR

– – – WDCE WDE WDP2 WDP1 WDP0 52

0x20

(2)

(0x40)

(2)

UBRR0H URSEL0 – – – UBRR0[11:8] 189

UCSR0C URSEL0 UMSEL0 UPM01 UPM00 USBS0 UCSZ01 UCSZ00 UCPOL0 188

0x1F (0x3F) EEARH

– – – – – – – EEAR8 18

0x1E (0x3E) EEARL EEPROM Address Register Low Byte 18

0x1D (0x3D) EEDR EEPROM Data Register 19

0x1C (0x3C) EECR

– – – – EERIE EEMWE EEWE EERE 19

0x1B (0x3B) PORTA PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 81

0x1A (0x3A) DDRA DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 81

0x19 (0x39) PINA PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 81

0x18 (0x38) PORTB PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 81

0x17 (0x37) DDRB DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 81

0x16 (0x36) PINB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 81

0x15 (0x35) PORTC PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 81

0x14 (0x34) DDRC DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 81

0x13 (0x33) PINC PINC7 PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 82

0x12 (0x32) PORTD PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 82

0x11 (0x31) DDRD DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 82

0x10 (0x30) PIND PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 82

0x0F (0x2F) SPDR SPI Data Register 163

0x0E (0x2E) SPSR SPIF WCOL

– – – – – SPI2X 163

0x0D (0x2D) SPCR SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 161

0x0C (0x2C) UDR0 USART0 I/O Data Register 185

0x0B (0x2B) UCSR0A RXC0 TXC0 UDRE0 FE0 DOR0 UPE0 U2X0 MPCM0 185

0x0A (0x2A) UCSR0B RXCIE0 TXCIE0 UDRIE0 RXEN0 TXEN0 UCSZ02 RXB80 TXB80 186

0x09 (0x29) UBRR0L USART0 Baud Rate Register Low Byte 189

0x08 (0x28) ACSR ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 194

0x07 (0x27) PORTE

– – – – – PORTE2 PORTE1 PORTE0 82

0x06 (0x26) DDRE

– – – – – DDE2 DDE1 DDE0 82

0x05 (0x25) PINE

– – – – – PINE2 PINE1 PINE0 82

0x04

(1)

(0x24)

(1)

OSCCAL – CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 37

OCDR On-chip Debug Register 201

0x03 (0x23) UDR1 USART1 I/O Data Register 185

0x02 (0x22) UCSR1A RXC1 TXC1 UDRE1 FE1 DOR1 UPE1 U2X1 MPCM1 185

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page