User guide
Table Of Contents
- Features
- Pin Configurations
- Overview
- AVR CPU Core
- AVR ATmega162 Memories
- System Clock and Clock Options
- Power Management and Sleep Modes
- System Control and Reset
- Interrupts
- I/O-Ports
- Introduction
- Ports as General Digital I/O
- Alternate Port Functions
- Register Description for I/O-Ports
- Port A Data Register – PORTA
- Port A Data Direction Register – DDRA
- Port A Input Pins Address – PINA
- Port B Data Register – PORTB
- Port B Data Direction Register – DDRB
- Port B Input Pins Address – PINB
- Port C Data Register – PORTC
- Port C Data Direction Register – DDRC
- Port C Input Pins Address – PINC
- Port D Data Register – PORTD
- Port D Data Direction Register – DDRD
- Port D Input Pins Address – PIND
- Port E Data Register – PORTE
- Port E Data Direction Register – DDRE
- Port E Input Pins Address – PINE
- External Interrupts
- 8-bit Timer/Counter0 with PWM
- Timer/Counter0, Timer/Counter1, and Timer/Counter3 Prescalers
- 16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3)
- Restriction in ATmega161 Compatibility Mode
- Overview
- Accessing 16-bit Registers
- Timer/Counter Clock Sources
- Counter Unit
- Input Capture Unit
- Output Compare Units
- Compare Match Output Unit
- Modes of Operation
- Timer/Counter Timing Diagrams
- 16-bit Timer/Counter Register Description
- Timer/Counter1 Control Register A – TCCR1A
- Timer/Counter3 Control Register A – TCCR3A
- Timer/Counter1 Control Register B – TCCR1B
- Timer/Counter3 Control Register B – TCCR3B
- Timer/Counter1 – TCNT1H and TCNT1L
- Timer/Counter3 – TCNT3H and TCNT3L
- Output Compare Register 1 A – OCR1AH and OCR1AL
- Output Compare Register 1 B – OCR1BH and OCR1BL
- Output Compare Register 3 A – OCR3AH and OCR3AL
- Output Compare Register 3 B – OCR3BH and OCR3BL
- Input Capture Register 1 – ICR1H and ICR1L
- Input Capture Register 3 – ICR3H and ICR3L
- Timer/Counter Interrupt Mask Register – TIMSK(1)
- Extended Timer/Counter Interrupt Mask Register – ETIMSK(1)
- Timer/Counter Interrupt Flag Register – TIFR(1)
- Extended Timer/Counter Interrupt Flag Register – ETIFR(1)
- 8-bit Timer/Counter2 with PWM and Asynchronous operation
- Serial Peripheral Interface – SPI
- USART
- Analog Comparator
- JTAG Interface and On-chip Debug System
- IEEE 1149.1 (JTAG) Boundary-scan
- Boot Loader Support – Read-While-Write Self-programming
- Features
- Application and Boot Loader Flash Sections
- Read-While-Write and No Read-While-Write Flash Sections
- Boot Loader Lock Bits
- Entering the Boot Loader Program
- Addressing the Flash During Self- programming
- Self-programming the Flash
- Performing Page Erase by SPM
- Filling the Temporary Buffer (Page Loading)
- Performing a Page Write
- Using the SPM Interrupt
- Consideration while Updating BLS
- Prevent Reading the RWW Section During Self- programming
- Setting the Boot Loader Lock Bits by SPM
- EEPROM Write Prevents Writing to SPMCR
- Reading the Fuse and Lock Bits from Software
- Preventing Flash Corruption
- Programming Time for Flash When Using SPM
- Simple Assembly Code Example for a Boot Loader
- ATmega162 Boot Loader Parameters
- Memory Programming
- Program And Data Memory Lock Bits
- Fuse Bits
- Signature Bytes
- Calibration Byte
- Parallel Programming Parameters, Pin Mapping, and Commands
- Parallel Programming
- Enter Programming Mode
- Considerations for Efficient Programming
- Chip Erase
- Programming the Flash
- Programming the EEPROM
- Reading the Flash
- Reading the EEPROM
- Programming the Fuse Low Bits
- Programming the Fuse High Bits
- Programming the Extended Fuse Bits
- Programming the Lock Bits
- Reading the Fuse and Lock Bits
- Reading the Signature Bytes
- Reading the Calibration Byte
- Parallel Programming Characteristics
- Serial Downloading
- SPI Serial Programming Pin Mapping
- Programming via the JTAG Interface
- Programming Specific JTAG Instructions
- AVR_RESET (0xC)
- PROG_ENABLE (0x4)
- PROG_COMMANDS (0x5)
- PROG_PAGELOAD (0x6)
- PROG_PAGEREAD (0x7)
- Data Registers
- Reset Register
- Programming Enable Register
- Programming Command Register
- Virtual Flash Page Load Register
- Virtual Flash Page Read Register
- Programming Algorithm
- Entering Programming Mode
- Leaving Programming Mode
- Performing Chip Erase
- Programming the Flash
- Reading the Flash
- Programming the EEPROM
- Reading the EEPROM
- Programming the Fuses
- Programming the Lock Bits
- Reading the Fuses and Lock Bits
- Reading the Signature Bytes
- Reading the Calibration Byte
- Electrical Characteristics
- ATmega162 Typical Characteristics
- Active Supply Current
- Idle Supply Current
- Power-down Supply Current
- Power-save Supply Current
- Standby Supply Current
- Pin Pull-up
- Pin Driver Strength
- Pin Thresholds and Hysteresis
- BOD Thresholds and Analog Comparator Offset
- Internal Oscillator Speed
- Current Consumption of Peripheral Units
- Current Consumption in Reset and Reset Pulsewidth
- Register Summary
- Instruction Set Summary
- Ordering Information
- Packaging Information
- Erratas
- Datasheet Change Log for ATmega162
- Table of Contents
264
ATmega162/V
2513E–AVR–09/03
Notes: 1. “Max” means the highest value where the pin is guaranteed to be read as low
2. “Min” means the lowest value where the pin is guaranteed to be read as high
3. Although each I/O port can sink more than the test conditions (20 mA at Vcc = 5V, 10 mA at Vcc = 3V) under steady state
conditions (non-transient), the following must be observed:
PDIP Package:
1] The sum of all IOL, for all ports, should not exceed 300 mA.
2] The sum of all IOL, for port B0 - B7, D0 - D7, and XTAL2, should not exceed 150 mA.
3] The sum of all IOL, for ports A0 - A7, E0 - E2, C0 - C7, should not exceed 150 mA.
TQFP and MLF Package:
1] The sum of all IOL, for all ports, should not exceed 400 mA.
2] The sum of all IOL, for ports B0 - B7, D0 - D7, and XTAL2, should not exceed 200 mA.
3] The sum of all IOL, for ports C0 - C7 and E1 - E2, should not exceed 200 mA.
4] The sum of all IOL, for ports A0 - A7 and E0, should not exceed 200 mA.
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test condition.
4. Although each I/O port can source more than the test conditions (20 mA at Vcc = 5V, 10 mA at Vcc = 3V) under steady state
conditions (non-transient), the following must be observed:
PDIP Package:
1] The sum of all IOH, for all ports, should not exceed 300 mA.
2] The sum of all IOH, for port B0 - B7, D0 - D7, and XTAL2, should not exceed 150 mA.
3] The sum of all IOH, for ports A0 - A7, E0 - E2, C0 - C7, should not exceed 150 mA.
TQFP and MLF Package:
1] The sum of all IOH, for all ports, should not exceed 400 mA.
2] The sum of all IOH, for ports B0 - B7, D0 - D7, and XTAL2, should not exceed 200 mA.
3] The sum of all IOH, for ports C0 - C7 and E1 - E2, should not exceed 200 mA.
4] The sum of all IOH, for ports A0 - A7 and E0, should not exceed 200 mA.
If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current
greater than the listed test condition.
I
CC
Power Supply Current
Active 1 MHz, V
CC
= 2V
(ATmega162V)
0.8 mA
Active 4 MHz, V
CC
= 3V
(ATmega162/V)
5mA
Active 8 MHz, V
CC
= 5V
(ATmega162)
16 mA
Idle 1 MHz, V
CC
= 2V
(ATmega162V)
0.3 mA
Idle 4 MHz, V
CC
= 3V
(ATmega162/V)
2mA
Idle 8 MHz, V
CC
= 5V
(ATmega162)
8mA
Power-down mode
WDT Enabled,
V
CC
= 3.0V
< 10 14 µA
WDT Disabled,
V
CC
= 3.0V
< 1.5 2 µA
V
ACIO
Analog Comparator Input Offset
Voltage
V
CC
= 5V
V
in
= V
CC
/2
< 10 40 mV
I
ACLK
Analog Comparator Input Leakage
Current
V
CC
= 5V
V
in
= V
CC
/2
-50 50 nA
t
ACID
Analog Comparator Propagation
Delay
V
CC
= 2.7V
V
CC
= 4.0V
750
500
ns
T
A
= -40°C to 85°C, V
CC
= 1.8V to 5.5V (unless otherwise noted) (Continued)
Symbol Parameter Condition Min. Typ. Max. Units