User guide
Table Of Contents
- Features
- Pin Configurations
- Overview
- AVR CPU Core
- AVR ATmega162 Memories
- System Clock and Clock Options
- Power Management and Sleep Modes
- System Control and Reset
- Interrupts
- I/O-Ports
- Introduction
- Ports as General Digital I/O
- Alternate Port Functions
- Register Description for I/O-Ports
- Port A Data Register – PORTA
- Port A Data Direction Register – DDRA
- Port A Input Pins Address – PINA
- Port B Data Register – PORTB
- Port B Data Direction Register – DDRB
- Port B Input Pins Address – PINB
- Port C Data Register – PORTC
- Port C Data Direction Register – DDRC
- Port C Input Pins Address – PINC
- Port D Data Register – PORTD
- Port D Data Direction Register – DDRD
- Port D Input Pins Address – PIND
- Port E Data Register – PORTE
- Port E Data Direction Register – DDRE
- Port E Input Pins Address – PINE
- External Interrupts
- 8-bit Timer/Counter0 with PWM
- Timer/Counter0, Timer/Counter1, and Timer/Counter3 Prescalers
- 16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3)
- Restriction in ATmega161 Compatibility Mode
- Overview
- Accessing 16-bit Registers
- Timer/Counter Clock Sources
- Counter Unit
- Input Capture Unit
- Output Compare Units
- Compare Match Output Unit
- Modes of Operation
- Timer/Counter Timing Diagrams
- 16-bit Timer/Counter Register Description
- Timer/Counter1 Control Register A – TCCR1A
- Timer/Counter3 Control Register A – TCCR3A
- Timer/Counter1 Control Register B – TCCR1B
- Timer/Counter3 Control Register B – TCCR3B
- Timer/Counter1 – TCNT1H and TCNT1L
- Timer/Counter3 – TCNT3H and TCNT3L
- Output Compare Register 1 A – OCR1AH and OCR1AL
- Output Compare Register 1 B – OCR1BH and OCR1BL
- Output Compare Register 3 A – OCR3AH and OCR3AL
- Output Compare Register 3 B – OCR3BH and OCR3BL
- Input Capture Register 1 – ICR1H and ICR1L
- Input Capture Register 3 – ICR3H and ICR3L
- Timer/Counter Interrupt Mask Register – TIMSK(1)
- Extended Timer/Counter Interrupt Mask Register – ETIMSK(1)
- Timer/Counter Interrupt Flag Register – TIFR(1)
- Extended Timer/Counter Interrupt Flag Register – ETIFR(1)
- 8-bit Timer/Counter2 with PWM and Asynchronous operation
- Serial Peripheral Interface – SPI
- USART
- Analog Comparator
- JTAG Interface and On-chip Debug System
- IEEE 1149.1 (JTAG) Boundary-scan
- Boot Loader Support – Read-While-Write Self-programming
- Features
- Application and Boot Loader Flash Sections
- Read-While-Write and No Read-While-Write Flash Sections
- Boot Loader Lock Bits
- Entering the Boot Loader Program
- Addressing the Flash During Self- programming
- Self-programming the Flash
- Performing Page Erase by SPM
- Filling the Temporary Buffer (Page Loading)
- Performing a Page Write
- Using the SPM Interrupt
- Consideration while Updating BLS
- Prevent Reading the RWW Section During Self- programming
- Setting the Boot Loader Lock Bits by SPM
- EEPROM Write Prevents Writing to SPMCR
- Reading the Fuse and Lock Bits from Software
- Preventing Flash Corruption
- Programming Time for Flash When Using SPM
- Simple Assembly Code Example for a Boot Loader
- ATmega162 Boot Loader Parameters
- Memory Programming
- Program And Data Memory Lock Bits
- Fuse Bits
- Signature Bytes
- Calibration Byte
- Parallel Programming Parameters, Pin Mapping, and Commands
- Parallel Programming
- Enter Programming Mode
- Considerations for Efficient Programming
- Chip Erase
- Programming the Flash
- Programming the EEPROM
- Reading the Flash
- Reading the EEPROM
- Programming the Fuse Low Bits
- Programming the Fuse High Bits
- Programming the Extended Fuse Bits
- Programming the Lock Bits
- Reading the Fuse and Lock Bits
- Reading the Signature Bytes
- Reading the Calibration Byte
- Parallel Programming Characteristics
- Serial Downloading
- SPI Serial Programming Pin Mapping
- Programming via the JTAG Interface
- Programming Specific JTAG Instructions
- AVR_RESET (0xC)
- PROG_ENABLE (0x4)
- PROG_COMMANDS (0x5)
- PROG_PAGELOAD (0x6)
- PROG_PAGEREAD (0x7)
- Data Registers
- Reset Register
- Programming Enable Register
- Programming Command Register
- Virtual Flash Page Load Register
- Virtual Flash Page Read Register
- Programming Algorithm
- Entering Programming Mode
- Leaving Programming Mode
- Performing Chip Erase
- Programming the Flash
- Reading the Flash
- Programming the EEPROM
- Reading the EEPROM
- Programming the Fuses
- Programming the Lock Bits
- Reading the Fuses and Lock Bits
- Reading the Signature Bytes
- Reading the Calibration Byte
- Electrical Characteristics
- ATmega162 Typical Characteristics
- Active Supply Current
- Idle Supply Current
- Power-down Supply Current
- Power-save Supply Current
- Standby Supply Current
- Pin Pull-up
- Pin Driver Strength
- Pin Thresholds and Hysteresis
- BOD Thresholds and Analog Comparator Offset
- Internal Oscillator Speed
- Current Consumption of Peripheral Units
- Current Consumption in Reset and Reset Pulsewidth
- Register Summary
- Instruction Set Summary
- Ordering Information
- Packaging Information
- Erratas
- Datasheet Change Log for ATmega162
- Table of Contents
232
ATmega162/V
2513E–AVR–09/03
Notes: 1. The SPIEN Fuse is not accessible in SPI Serial Programming mode.
2. The default value of BOOTSZ1:0 results in maximum Boot Size. See Table 94 on
page 228 for details.
3. Never ship a product with the OCDEN Fuse programmed regardless of the setting of
Lock bits and the JTAGEN Fuse. A programmed OCDEN Fuse enables some parts of
the clock system to be running in all sleep modes. This may increase the power
consumption.
4. If the JTAG interface is left unconnected, the JTAGEN fuse should if possible be dis-
abled. This to avoid static current at the TDO pin in the JTAG interface.
Notes: 1. The default value of SUT1:0 results in maximum start-up time for the default clock
source. See Table 12 on page 37 for details.
2. The default setting of CKSEL3:0 results in Internal RC Oscillator @ 8 MHz. See
Table 5 on page 34 for details.
3. The CKOUT Fuse allow the system clock to be output on PortB 0. See “Clock output
buffer” on page 38 for details.
4. See “System Clock Prescaler” on page 39 for details.
The status of the Fuse bits is not affected by Chip Erase. Note that the Fuse bits are
locked if Lock bit1 (LB1) is programmed. Program the Fuse bits before programming the
Lock bits.
Table 100. Fuse High Byte
Fuse Low Byte Bit no Description Default Value
OCDEN
(3)
7 Enable OCD
1 (unprogrammed, OCD
disabled)
JTAGEN
(4)
6 Enable JTAG
0 (programmed, JTAG
enabled)
SPIEN
(1)
5
Enable Serial Program and Data
Downloading
0 (programmed, SPI prog.
enabled)
WDTON 4 Watchdog Timer always on 1 (unprogrammed)
EESAVE 3
EEPROM memory is preserved
through the Chip Erase
1 (unprogrammed,
EEPROM not preserved)
BOOTSZ1 2
Select Boot Size (see Table 94 for
details)
0 (programmed)
(2)
BOOTSZ0 1
Select Boot Size (see Table 94 for
details)
0 (programmed)
(2)
BOOTRST 0 Select Reset Vector 1 (unprogrammed)
Table 101. Fuse Low Byte
Fuse Low Byte Bit no Description Default value
CKDIV8
(4)
7 Divide clock by 8 0 (programmed)
CKOUT
(3)
6 Clock Output 1 (unprogrammed)
SUT1 5 Select start-up time 1 (unprogrammed)
(1)
SUT0 4 Select start-up time 0 (programmed)
(1)
CKSEL3 3 Select Clock source 0 (programmed)
(2)
CKSEL2 2 Select Clock source 0 (programmed)
(2)
CKSEL1 1 Select Clock source 1 (unprogrammed)
(2)
CKSEL0 0 Select Clock source 0 (programmed)
(2)