User guide

17
ATmega162/V
2513E–AVR–09/03
When using register indirect addressing modes with automatic pre-decrement and post-
increment, the address registers X, Y, and Z are decremented or incremented.
The 32 general purpose working registers, 64 (+160) I/O Registers, and the 1024 bytes
of internal data SRAM in the ATmega162 are all accessible through all these addressing
modes. The Register File is described in “General Purpose Register File” on page 10.
Figure 9. Data Memory Map
Data Memory Access Times This section describes the general access timing concepts for internal memory access.
The internal data SRAM access is performed in two clk
CPU
cycles as described in Figure
10.
Figure 10. On-chip Data SRAM Access Cycles
32 Registers
64 I/O Registers
Internal SRAM
(1024 x 8)
0x0000 - 0x001F
0x0020 - 0x005F
0x0460
0x045F
0xFFFF
0x0060
Data Memory
External SRAM
(0 - 64K x 8)
Memory configuration B
32 Registers
64 I/O Registers
Internal SRAM
(1024 x 8)
0x0000 - 0x001F
0x0020 - 0x005F
0x04FF
0xFFFF
0x0060 - 0x00FF
Data Memory
External SRAM
(0 - 64K x 8)
Memory configuration A
160 Ext I/O Reg.
0x0100
0x0500
clk
WR
RD
Data
Data
Address
Address valid
T1 T2 T3
Compute Address
Read
Write
CPU
Memory Access Instruction
Next Instruction