User guide
Table Of Contents
- Features
- Pin Configurations
- Overview
- AVR CPU Core
- AVR ATmega162 Memories
- System Clock and Clock Options
- Power Management and Sleep Modes
- System Control and Reset
- Interrupts
- I/O-Ports
- Introduction
- Ports as General Digital I/O
- Alternate Port Functions
- Register Description for I/O-Ports
- Port A Data Register – PORTA
- Port A Data Direction Register – DDRA
- Port A Input Pins Address – PINA
- Port B Data Register – PORTB
- Port B Data Direction Register – DDRB
- Port B Input Pins Address – PINB
- Port C Data Register – PORTC
- Port C Data Direction Register – DDRC
- Port C Input Pins Address – PINC
- Port D Data Register – PORTD
- Port D Data Direction Register – DDRD
- Port D Input Pins Address – PIND
- Port E Data Register – PORTE
- Port E Data Direction Register – DDRE
- Port E Input Pins Address – PINE
- External Interrupts
- 8-bit Timer/Counter0 with PWM
- Timer/Counter0, Timer/Counter1, and Timer/Counter3 Prescalers
- 16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3)
- Restriction in ATmega161 Compatibility Mode
- Overview
- Accessing 16-bit Registers
- Timer/Counter Clock Sources
- Counter Unit
- Input Capture Unit
- Output Compare Units
- Compare Match Output Unit
- Modes of Operation
- Timer/Counter Timing Diagrams
- 16-bit Timer/Counter Register Description
- Timer/Counter1 Control Register A – TCCR1A
- Timer/Counter3 Control Register A – TCCR3A
- Timer/Counter1 Control Register B – TCCR1B
- Timer/Counter3 Control Register B – TCCR3B
- Timer/Counter1 – TCNT1H and TCNT1L
- Timer/Counter3 – TCNT3H and TCNT3L
- Output Compare Register 1 A – OCR1AH and OCR1AL
- Output Compare Register 1 B – OCR1BH and OCR1BL
- Output Compare Register 3 A – OCR3AH and OCR3AL
- Output Compare Register 3 B – OCR3BH and OCR3BL
- Input Capture Register 1 – ICR1H and ICR1L
- Input Capture Register 3 – ICR3H and ICR3L
- Timer/Counter Interrupt Mask Register – TIMSK(1)
- Extended Timer/Counter Interrupt Mask Register – ETIMSK(1)
- Timer/Counter Interrupt Flag Register – TIFR(1)
- Extended Timer/Counter Interrupt Flag Register – ETIFR(1)
- 8-bit Timer/Counter2 with PWM and Asynchronous operation
- Serial Peripheral Interface – SPI
- USART
- Analog Comparator
- JTAG Interface and On-chip Debug System
- IEEE 1149.1 (JTAG) Boundary-scan
- Boot Loader Support – Read-While-Write Self-programming
- Features
- Application and Boot Loader Flash Sections
- Read-While-Write and No Read-While-Write Flash Sections
- Boot Loader Lock Bits
- Entering the Boot Loader Program
- Addressing the Flash During Self- programming
- Self-programming the Flash
- Performing Page Erase by SPM
- Filling the Temporary Buffer (Page Loading)
- Performing a Page Write
- Using the SPM Interrupt
- Consideration while Updating BLS
- Prevent Reading the RWW Section During Self- programming
- Setting the Boot Loader Lock Bits by SPM
- EEPROM Write Prevents Writing to SPMCR
- Reading the Fuse and Lock Bits from Software
- Preventing Flash Corruption
- Programming Time for Flash When Using SPM
- Simple Assembly Code Example for a Boot Loader
- ATmega162 Boot Loader Parameters
- Memory Programming
- Program And Data Memory Lock Bits
- Fuse Bits
- Signature Bytes
- Calibration Byte
- Parallel Programming Parameters, Pin Mapping, and Commands
- Parallel Programming
- Enter Programming Mode
- Considerations for Efficient Programming
- Chip Erase
- Programming the Flash
- Programming the EEPROM
- Reading the Flash
- Reading the EEPROM
- Programming the Fuse Low Bits
- Programming the Fuse High Bits
- Programming the Extended Fuse Bits
- Programming the Lock Bits
- Reading the Fuse and Lock Bits
- Reading the Signature Bytes
- Reading the Calibration Byte
- Parallel Programming Characteristics
- Serial Downloading
- SPI Serial Programming Pin Mapping
- Programming via the JTAG Interface
- Programming Specific JTAG Instructions
- AVR_RESET (0xC)
- PROG_ENABLE (0x4)
- PROG_COMMANDS (0x5)
- PROG_PAGELOAD (0x6)
- PROG_PAGEREAD (0x7)
- Data Registers
- Reset Register
- Programming Enable Register
- Programming Command Register
- Virtual Flash Page Load Register
- Virtual Flash Page Read Register
- Programming Algorithm
- Entering Programming Mode
- Leaving Programming Mode
- Performing Chip Erase
- Programming the Flash
- Reading the Flash
- Programming the EEPROM
- Reading the EEPROM
- Programming the Fuses
- Programming the Lock Bits
- Reading the Fuses and Lock Bits
- Reading the Signature Bytes
- Reading the Calibration Byte
- Electrical Characteristics
- ATmega162 Typical Characteristics
- Active Supply Current
- Idle Supply Current
- Power-down Supply Current
- Power-save Supply Current
- Standby Supply Current
- Pin Pull-up
- Pin Driver Strength
- Pin Thresholds and Hysteresis
- BOD Thresholds and Analog Comparator Offset
- Internal Oscillator Speed
- Current Consumption of Peripheral Units
- Current Consumption in Reset and Reset Pulsewidth
- Register Summary
- Instruction Set Summary
- Ordering Information
- Packaging Information
- Erratas
- Datasheet Change Log for ATmega162
- Table of Contents
168
ATmega162/V
2513E–AVR–09/03
Signal description:
txclk Transmitter clock. (Internal Signal)
rxclk Receiver base clock. (Internal Signal)
xcki Input from XCK pin (internal Signal). Used for synchronous slave operation.
xcko Clock output to XCK pin (Internal Signal). Used for synchronous master
operation.
fosc XTAL pin frequency (System Clock).
Internal Clock Generation –
The Baud Rate Generator
Internal clock generation is used for the asynchronous and the synchronous master
modes of operation. The description in this section refers to Figure 76.
The USART Baud Rate Register (UBRR) and the down-counter connected to it function
as a programmable prescaler or baud rate generator. The down-counter, running at sys-
tem clock (fosc), is loaded with the UBRR value each time the counter has counted
down to zero or when the UBRRL Register is written. A clock is generated each time the
counter reaches zero. This clock is the baud rate generator clock output (=
fosc/(UBRR+1)). The Transmitter divides the baud rate generator clock output by 2, 8 or
16 depending on mode. The baud rate generator output is used directly by the receiver’s
clock and data recovery units. However, the recovery units use a state machine that
uses 2, 8 or 16 states depending on mode set by the state of the UMSEL, U2X and
DDR_XCK bits.
Table 70 contains equations for calculating the baud rate (in bits per second) and for
calculating the UBRR value for each mode of operation using an internally generated
clock source.
Note: 1. The baud rate is defined to be the transfer rate in bit per second (bps).
BAUD Baud rate (in bits per second, bps)
f
OSC
System Oscillator clock frequency
UBRR Contents of the UBRRH and UBRRL Registers, (0 - 4095)
Some examples of UBRR values for some system clock frequencies are found in Table
78 (see page 190).
Table 70. Equations for Calculating Baud Rate Register Setting
Operating Mode
Equation for Calculating
Baud Rate
(1)
Equation for Calculating
UBRR Value
Asynchronous Normal Mode
(U2X = 0)
Asynchronous Double Speed
Mode (U2X = 1)
Synchronous Master Mode
BAUD
f
OSC
16 UBRR 1+()
---------------------------------------= UBRR
f
OSC
16BAUD
------------------------ 1–=
BAUD
f
OSC
8 UBRR 1+()
-----------------------------------= UBRR
f
OSC
8BAUD
-------------------- 1–=
BAUD
f
OSC
2 UBRR 1+()
-----------------------------------= UBRR
f
OSC
2BAUD
-------------------- 1–=