User guide

122
ATmega162/V
2513E–AVR–09/03
ICFn Flag is set accordingly at the same timer clock cycle as the OCRnx Registers are
updated with the double buffer value (at TOP). The Interrupt Flags can be used to gen-
erate an interrupt each time the counter reaches the TOP or BOTTOM value.
When changing the TOP value the program must ensure that the new TOP value is
higher or equal to the value of all of the compare registers. If the TOP value is lower
than any of the compare registers, a Compare Match will never occur between the
TCNTn and the OCRnx. Note that when using fixed TOP values, the unused bits are
masked to zero when any of the OCRnx Registers are written. As the third period shown
in Figure 53 illustrates, changing the TOP actively while the Timer/Counter is running in
the phase correct mode can result in an unsymmetrical output. The reason for this can
be found in the time of update of the OCRnx Register. Since the OCRnx update occurs
at TOP, the PWM period starts and ends at TOP. This implies that the length of the fall-
ing slope is determined by the previous TOP value, while the length of the rising slope is
determined by the new TOP value. When these two values differ the two slopes of the
period will differ in length. The difference in length gives the unsymmetrical result on the
output.
It is recommended to use the phase and frequency correct mode instead of the phase
correct mode when changing the TOP value while the Timer/Counter is running. When
using a static TOP value there are practically no differences between the two modes of
operation.
In phase correct PWM mode, the compare units allow generation of PWM waveforms on
the OCnx pins. Setting the COMnx1:0 bits to two will produce a non-inverted PWM and
an inverted PWM output can be generated by setting the COMnx1:0 to three (See Table
55 on page 128). The actual OCnx value will only be visible on the port pin if the data
direction for the port pin is set as output (DDR_OCnx). The PWM waveform is gener-
ated by setting (or clearing) the OCnx Register at the Compare Match between OCRnx
and TCNTn when the counter increments, and clearing (or setting) the OCnx Register at
Compare Match between OCRnx and TCNTn when the counter decrements. The PWM
frequency for the output when using phase correct PWM can be calculated by the fol-
lowing equation:
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). For
Timer/Counter3 also prescaler factors 16 and 32 are available.
The extreme values for the OCRnx Register represent special cases when generating a
PWM waveform output in the phase correct PWM mode. If the OCRnx is set equal to
BOTTOM the output will be continuously low and if set equal to TOP the output will be
continuously high for non-inverted PWM mode. For inverted PWM the output will have
the opposite logic values. If OCRnA is used to define the TOP value (WGMn3:0 = 11)
and COMnA1:0 = 1, the OCnA output will toggle with a 50% duty cycle.
Phase and Frequency Correct
PWM Mode
The phase and frequency correct Pulse Width Modulation, or phase and frequency cor-
rect PWM mode (WGMn3:0 = 8 or 9) provides a high resolution phase and frequency
correct PWM waveform generation option. The phase and frequency correct PWM
mode is, like the phase correct PWM mode, based on a dual-slope operation. The
counter counts repeatedly from BOTTOM (0x0000) to TOP and then from TOP to BOT-
TOM. In non-inverting Compare Output mode, the Output Compare (OCnx) is cleared
on the Compare Match between TCNTn and OCRnx while up-counting, and set on the
Compare Match while down-counting. In inverting Compare Output mode, the operation
is inverted. The dual-slope operation gives a lower maximum operation frequency com-
f
OCnxPCPWM
f
clk_I/O
2 NTOP⋅⋅
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