Manual

90
ATmega161(L)
1228C–AVR–08/02
Port A pins are tri-stated when a reset condition becomes active, even if the clock is not
running.
Note: 1. n: 7,6…0, pin number
Port A Schematics Note that all port pins are synchronized. The synchronization latch is, however, not
shown in the figure.
Figure 55. Port A Schematic Diagrams (Pins PA0 - PA7)
Table 29. DDAn Effects on Port A Pins
(1)
DDAn PORTAn I/O Pull-up Comment
0 0 Input No Tri-state (high-Z)
0 1 Input Yes PAn will source current if ext. pulled low.
1 0 Output No Push-pull Zero Output
1 1 Output No Push-pull One Output