Manual

85
ATmega161(L)
1228C–AVR–08/02
• Bits 3..2 EMCUCR – SRW01, SRW00: Wait State Select Bits for Lower Page
The SRW01 and SRW00 bits control the number of wait states for the lower page of the
external memory address space (see Table 27).
Note: 1. n = 0 or 1 (lower/upper page)
For further details of the timing and wait states of the external memory interface, see
Figure 50 through Figure 53 for how the setting of the SRW bits affects the timing.
Table 27. Wait States
(1)
SRWn1 SRWn0 Wait States
0 0 No wait states
0 1 Wait one cycle during read/write strobe
1 0 Wait two cycles during read/write strobe
1 1 Wait two cycles during read/write and wait one cycle before driving
out new address
Table 28. Page Limits with Different Settings of SRL2..0
SRL2 SRL1 SRL0 Page Limits
000
Lower page = N/A
Upper page = $0460-$FFFF
001
Lower page = $0460-$1FFF
Upper page = $2000-$FFFF
010
Lower page = $0460-$4FFF
Upper page = $4000-$FFFF
011
Lower page = $0460-$5FFF
Upper page = $6000-$FFFF
100
Lower page = $0460-$7FFF
Upper page = $8000-$FFFF
101
Lower page = $0460-$9FFF
Upper page = $A000-$FFFF
110
Lower page = $0460-$BFFF
Upper page = $C000-$FFFF
111
Lower page = $0460-$DFFF
Upper page = $E000-$FFFF