Manual

108
ATmega161(L)
1228C–AVR–08/02
Port E Schematics Figure 71. Port E Schematic Diagram (Pin PE0)
Figure 72. Port E Schematic Diagram (Pin PE1)
DATA BUS
D
D
Q
Q
RESET
RESET
C
C
WD
WP
RD
MOS
PULL-
UP
PE0
R
R
WP:
WD:
RL:
RP:
RD:
ACIC:
ACO:
WRITE PORTE
WRITE DDRE
READ PORTE LATCH
READ PORTE PIN
READ DDRE
COMPARATOR IC ENABLE
COMPARATOR OUTPUT
DDE0
PORTE0
NOISE CANCELER EDGE SELECT ICF1
ICNC1 ICES1
0
1
ACIC
ACO
RL
RP
DQ
C
R
PORTE0
ISC2
'1'
INT2
SW CLEAR
HW CLEAR
DATA BUS
D
D
Q
Q
RESET
RESET
C
C
WD
WP
RD
MOS
PULL-
UP
PE1
R
R
WP:
WD:
RL:
RP:
RD:
SRE:
WRITE PORTE
WRITE DDRE
READ PORTE LATCH
READ PORTE PIN
READ DDRE
DDE1
PORTE1
RL
RP
SRE
ALE
XRAM ENABLE
ALE: ALE PULSE FROM XRAM