Features • High-performance, Low-power AVR® 8-bit Microcontroller • Advanced RISC Architecture • • • • • • • • – 130 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 8 MIPS Throughput at 8 MHz – On-chip 2-cycle Multiplier Program and Data Memories – 16K Bytes of Non-volatile In-System Programmable Flash Endurance: 1,000 Write/Erase Cycles – Optional Boot Code Memory with Independent Lock bits Self-programming of Progr
Pin Configuration PDIP (OC0/T0) PB0 (OC2/T1) PB1 (RXD1/AIN0) PB2 (TXD1/AIN1) PB3 (SS) PB4 (MOSI) PB5 (MISO) PB6 (SCK) PB7 RESET (RXD0) PD0 (TXD0) PD1 (INT0) PD2 (INT1) PD3 (TOSC1) PD4 (OC1A/TOSC2) PD5 (WR) PD6 (RD) PD7 XTAL2 XTAL1 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC PA0 (AD0) PA1 (AD1) PA2 (AD2) PA3 (AD3) PA4 (AD4) PA5 (AD5) PA6 (AD6) PA7 (AD7) PE0 (ICP/INT2) PE1 (ALE) PE2 (OC1B) PC7 (A15) PC6 (A14) PC5 (A13) PC4 (A12) PC
ATmega161(L) Description The ATmega161 is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega161 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. The AVR core combines a rich instruction set with 32 general purpose working registers.
Block Diagram Figure 1. The ATmega161 Block Diagram PA0-PA7 PC0-PC7 PORTA DRIVERS PORTC DRIVERS VCC GND DATA REGISTER PORTA DATA DIR. REG. PORTA DATA REGISTER PORTC DATA DIR. REG.
ATmega161(L) Pin Descriptions VCC Supply voltage. GND Ground. Port A (PA7..PA0) Port A is an 8-bit bi-directional I/O port. Port pins can provide internal pull-up resistors (selected for each bit). The Port A output buffers can sink 20 mA and can drive LED displays directly. When pins PA0 to PA7 are used as inputs and are externally pulled low, they will source current if the internal pull-up resistors are activated.
Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier that can be configured for use as an on-chip Oscillator, as shown in Figure 2. Either a quartz crystal or a ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 3. Figure 2. Oscillator Connections C2 C1 XTAL2 XTAL1 GND Figure 3.
ATmega161(L) Architectural Overview The fast-access Register File concept contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This means that during one single clock cycle, one Arithmetic Logic Unit (ALU) operation is executed. Two operands are output from the Register File, the operation is executed and the result is stored back in the Register File – in one clock cycle.
In addition to the register operation, the conventional Memory Addressing modes can be used on the Register File. This is enabled by the fact that the Register File is assigned the 32 lowermost Data Space addresses ($00 - $1F), allowing them to be accessed as though they were ordinary memory locations. The I/O memory space contains 64 addresses for CPU peripheral functions such as Control Registers, Timer/Counters, and other I/O functions.
ATmega161(L) Figure 5. Memory Maps Data Memory Program Memory $000 32 Gen. Purpose $0000 Working Registers $001F $0020 64 I/O Registers Program Flash (8K x 16) $005F $0060 Internal SRAM (1024 x 8) $045F $0460 External SRAM (0 - 63K x 8) $1FFF $FFFF A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the Status Register.
The General Purpose Register File Figure 6 shows the structure of the 32 general purpose working registers in the CPU. Figure 6. AVR CPU General Purpose Working Registers 7 0 Addr.
ATmega161(L) In the different Addressing modes, these address registers have functions as fixed displacement, automatic increment and decrement (see the descriptions for the different instructions). ALU – Arithmetic Logic Unit The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, ALU operations between registers in the Register File are executed.
SRAM Data Memory Figure 8 shows how the ATmega161 SRAM memory is organized. Figure 8. SRAM Organization Register File Data Address Space R0 $0000 R1 $0001 R2 $0002 … … R29 $001D R30 $001E R31 $001F I/O Registers $00 $0020 $01 $0021 $02 $0022 … … $3D $005D $3E $005E $3F $005F Internal SRAM $0060 $0061 … $045E $045F The lower 1120 Data memory locations address the Register File, the I/O memory and the internal data SRAM.
ATmega161(L) The five different Addressing modes for the Data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-decrement and Indirect with Post-increment. In the Register File, registers R26 to R31 feature the indirect Addressing Pointer Registers. The direct addressing reaches the entire data space. The Indirect with Displacement mode features a 63-address locations reach from the base address given by the Y- or Z-register.
Operands are contained in registers r (Rr) and d (Rd). The result is stored in register d (Rd). I/O Direct Figure 11. I/O Direct Addressing I/O MEMORY 0 15 5 OP n 0 P 63 Operand address is contained in six bits of the instruction word. n is the destination or Source Register Address. Data Direct Figure 12. Direct Data Addressing Data Space 20 19 31 OP 16 $0000 Rr/Rd 16 LSBs 15 0 $FFFF A 16-bit data address is contained in the 16 LSBs of a two-word instruction.
ATmega161(L) Data Indirect with Displacement Figure 13. Data Indirect with Displacement Data Space $0000 15 0 Y OR Z - REGISTER 15 10 OP 6 5 n 0 a $FFFF Operand address is the result of the Y- or Z-register contents added to the address contained in six bits of the instruction word. Data Indirect Figure 14. Data Indirect Addressing Data Space $0000 15 0 X, Y, OR Z - REGISTER $FFFF Operand address is the contents of the X-, Y-, or Z-register. Data Indirect with Predecrement Figure 15.
Data Indirect with Postincrement Figure 16. Data Indirect Addressing with Post-increment Data Space $0000 15 0 X, Y, OR Z - REGISTER 1 $FFFF The X-, Y-, or Z-register is incremented after the operation. Operand address is the contents of the X-, Y-, or Z-register prior to incrementing. Constant Addressing Using the LPM Instruction Figure 17. Code Memory Constant Addressing PROGRAM MEMORY $000 15 1 0 Z-REGISTER $1FFF Constant byte address is specified by the Z-register contents.
ATmega161(L) Program execution continues at address contained by the Z-register (i.e., the PC is loaded with the contents of the Z-register). Relative Program Addressing, RJMP and RCALL Figure 19. Relative Program Memory Addressing PROGRAM MEMORY $000 15 0 PC 15 0 12 11 OP k $1FFF Program execution continues at address PC + k + 1. The relative address k is -2048 to 2047. Direct Program Addressing, JMP and CALL Figure 20.
Figure 21. The Parallel Instruction Fetches and Instruction Executions T1 T2 T3 T4 System Clock Ø 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch Figure 22 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed and the result is stored back to the destination register. Figure 22.
ATmega161(L) l/O Memory The I/O space definition of the ATmega161 is shown in Table 1. Table 1.
Table 1.
ATmega161(L) All ATmega161 I/Os and peripherals are placed in the I/O space. The I/O locations are accessed by the IN and OUT instructions transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range $00 $1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction set section for more details.
• Bit 2 – N: Negative Flag The Negative Flag N indicates a negative result after the different arithmetic and logic operations. See the Instruction Set description for detailed information. • Bit 1 – Z: Zero Flag The Zero Flag Z indicates a zero result after the different arithmetic and logic operations. See the Instruction Set description for detailed information. • Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation.
ATmega161(L) Table 2. Reset and Interrupt Vectors(1) Vector No.
$01a jmp UART_RXC0 ; UART0 RX Complete Handler $01c jmp UART_RXC1 ; UART1 RX Complete Handler $01e jmp UART_DRE0 ; UDR0 Empty Handler $020 jmp UART_DRE1 ; UDR1 Empty Handler $022 jmp UART_TXC0 ; UART0 TX Complete Handler $024 jmp UART_TXC1 ; UART1 TX Complete Handler $026 jmp EE_RDY ; EEPROM Ready Handler $028 jmp ANA_COMP ; Analog Comparator Handler ; $02a MAIN: ldi r16,high(RAMEND) ; Main program start $02b out SPH,r16 $02c ldi r16,low(RAMEND) $02d out SPL,r16 $02e
ATmega161(L) Reset Sources The ATmega161 has three sources of Reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (VPOT). • External Reset. The MCU is reset when a low level is present on the RESET pin for more than 500 ns. • Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and the Watchdog is enabled. During Reset, all I/O Registers are then set to their initial values and the program starts execution from address $000.
Table 3. Reset Characteristics (VCC = 5.0V)(1) Symbol Parameter Min Typ Max Units VPOT Power-on Reset Threshold Voltage (rising) 1.0 1.4 1.8 V Power-on Reset Threshold Voltage (falling)(1) 0.4 0.6 0.8 V 0.85 VCC V RESET Pin Threshold Voltage VRST Note: 1. The Power-on Reset will not work unless the supply voltage has been below VPOT (falling). ‘ Table 4. Reset Delay Selections(3) CKSEL [2:0] Start-up Time, VCC = 2.7V, SUT Unprogrammed Start-up Time, VCC = 4.
ATmega161(L) Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is nominally 1.4V (rising VCC). The POR is activated whenever V CC is below the detection level. The POR circuit can be used to trigger the Start-up Reset, as well as detect a failure in supply voltage. A Power-on Reset (POR) circuit ensures that the device is reset from Power-on.
External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than 500 ns will generate a Reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a Reset. When the applied signal reaches the Reset Threshold Voltage (VRST) on its positive edge, the delay timer starts the MCU after the Time-out period (tTOUT) has expired. Figure 27.
ATmega161(L) MCU Status Register – MCUSR The MCU Status Register provides information on which reset source caused an MCU Reset. Bit 7 6 5 4 3 2 1 0 $34 ($54) – – – – WDRF – EXTRF PORF Read/Write R R R R R/W R R/W R/W Initial Value 0 0 0 0 MCUSR See Bit Description • Bits 7..4 – Res: Reserved Bits These bits are reserved bits in the ATmega161 and always read as zero. • Bit 3 – WDRF: Watchdog Reset Flag This bit is set if a Watchdog Reset occurs.
Note that the Status Register is not automatically stored when entering an interrupt routine or restored when returning from an interrupt routine. This must be handled by software. Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. After four clock cycles, the Program Vector address for the actual interrupt handling routine is executed. During this four-clock-cycle period, the Program Counter (13 bits) is pushed onto the Stack.
ATmega161(L) • Bits 4..0 – Res: Reserved Bits These bits are reserved bits in the ATmega161 and always read as zero. General Interrupt Flag Register – GIFR Bit 7 6 5 4 3 2 1 $3A ($5A) INTF1 INTF0 INTF2 – – – – 0 – Read/Write R/W R/W R/W R R R R R Initial Value 0 0 0 0 0 0 0 0 GIFR • Bit 7 – INTF1: External Interrupt Flag1 When an event on the INT1 pin triggers an interrupt request, INTF1 becomes set (one).
• Bit 5 – OCIE1B: Timer/Counter1 Output CompareB Match Interrupt Enable When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareB Match interrupt is enabled. The corresponding interrupt (at Vector $010) is executed if a Compare B Match in Timer/Counter1 occurs, i.e., when the OCF1B bit is set in the Timer/Counter Interrupt Flag Register (TIFR).
ATmega161(L) Timer/Counter Interrupt Flag Register – TIFR Bit 7 6 5 4 3 2 1 0 $38 ($58) TOV1 OCF1A OCIFB TOV2 ICF1 OCF2 TOV0 OCF0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TIFR • Bit 7 – TOV1: Timer/Counter1 Overflow Flag The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by hardware when executing the corresponding Interrupt Handling Vector. Alternatively, TOV1 is cleared by writing a logical “1” to the Flag.
Compare match InterruptA Enable) and the OCF2 are set (one), the Timer/Counter2 Compare match Interrupt is executed. • Bit 1 – TOV0: Timer/Counter0 Overflow Flag The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding Interrupt Handling Vector. Alternatively, TOV0 is cleared by writing a logical “1” to the Flag.
ATmega161(L) grammer’s purpose, it is recommended to set the Sleep Enable (SE) bit just before the execution of the SLEEP instruction. • Bit 4 – SM1: Sleep Mode Select Bit 1 The SM1 bit, together with the SM0 control bit in EMCUCR, selects between the three available Sleep modes as shown in Table 6. Table 6.
Extended MCU Control Register – EMCUCR The Extended MCU Control Register contains control bits for External Interrupt 2, Sleep mode bit and control bits for the external memory interface.
ATmega161(L) Analog Comparator interrupt is not required, the Analog Comparator can be powered down by setting the ACD bit in the Analog Comparator Control and Status Register (ACSR). This will reduce power consumption in Idle mode. Power-down Mode When the SM1/SM0 bits are set to 10, the SLEEP instruction makes the MCU enter the Power-down mode. In this mode, the external Oscillator is stopped while the external interrupts and the Watchdog (if enabled) continue operating.
Timer/Counters The ATmega161 provides three general purpose Timer/Counters – two 8-bit T/Cs and one 16-bit T/C. Timer/Counter2 can optionally be asynchronously clocked from an external Oscillator. This Oscillator is optimized for use with a 32.768 kHz watch crystal, enabling use of Timer/Counter2 as a Real-time Clock (RTC). Timer/Counters 0 and 1 h ave ind ividua l p resca ling se le ction from the sa me 10 -bit pres caling timer. Timer/Counter2 has its own prescaler.
ATmega161(L) Figure 30. Timer/Counter2 Prescaler CK PCK2 PSR2 PCK2/1024 PCK2/256 PCK2/128 PCK2/32 PCK2/8 AS2 PCK2/64 10-BIT T/C PRESCALER Clear TOSC1 0 CS20 CS21 CS22 TIMER/COUNTER2 CLOCK SOURCE TCK2 The clock source for Timer/Counter2 prescaler is named PCK2. PCK2 is by default connected to the main system clock (CK). By setting the AS2 bit in ASSR, Timer/Counter2 is as yn ch ro no u sly c lo ck ed f ro m th e PD 4( TOS C1 ) pin .
• Bit 0 – PSR10: Prescaler Reset Timer/Counter1 and Timer/Counter0 When this bit is set (one), the Timer/Counter1 and Timer/Counter0 prescaler will be reset. The bit will be cleared by hardware after the operation is performed. Writing a zero to this bit will have no effect. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers. This bit will always be read as zero.
ATmega161(L) Figure 32. Timer/Counter2 Block Diagram T/C2 OVER- T/C2 COMPARE FLOW IRQ MATCH IRQ 8-BIT DATA BUS 0 TIMER/COUNTER2 (TCNT2) PSR2 PSR10 CS20 CS22 CS21 CTC2 COM21 COM20 FOC2 PWM2 TOV0 OCF0 ICF1 OCF2 TOV2 OCF1B SPECIAL FUNCTIONS IO REGISTER (SFIOR) T/C2 CONTROL REGISTER (TCCR2) TIMER INT. FLAG REGISTER (TIFR) TOV1 7 TOV2 OCF2 TIMER INT.
Timer/Counter0 Control Register – TCCR0 Bit 7 6 5 4 3 2 1 0 FOC0 PWM0 COM01 COM00 CTC0 CS02 CS01 CS00 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 $33 ($53) Timer/Counter2 Control Register – TCCR2 Bit 7 6 5 4 3 2 1 0 FOC2 PWM2 COM21 COM20 CTC2 CS22 CS21 CS20 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 $27 ($47) TCCR0 TCCR2 • Bit 7 – FOC0/FOC2: Force Output Compare Writing a lo
ATmega161(L) prescaling of 1 is used, and the compare register is set to C, the timer will count as follows if CTC0/CTC2 is set: ... | C-1 | C | 0 | 1 | ... When the prescaler is set to divide by 8, the timer will count like this: ... | C-1, C-1, C-1, C-1, C-1, C-1, C-1, C-1 | C, C, C, C, C, C, C, C | 0, 0, 0, 0, 0, 0, 0, 0 | 1, 1, 1, ... In PWM mode, this bit has a different function. If the CTC0 or CTC2 bit is cleared in PWM mode, the Timer/Counter acts as an up/down counter.
Timer Counter0 – TCNT0 Bit 7 6 5 4 3 2 1 0 $32 ($52) MSB LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 7 6 5 4 3 2 TCNT0 Timer/Counter2 – TCNT2 Bit 1 0 $23 ($43) MSB LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCNT2 These 8-bit registers contain the value of the Timer/Counters. Both Timer/Counters are realized as up or up/down (in PWM mode) counters with read and write access.
ATmega161(L) PWM Modes (Up/Down and Overflow) The two different PWM mod es are selected by the CTC0 or CTC 2 bit in the Timer/Counter Control Registers – TCCR0 or TCCR2, respectively. If CTC0/CTC2 is cleared and PWM mode is selected, the Timer/Counter acts as an up/down counter, counting up from $00 to $FF, where it turns and counts down again to zero before the cycle is repeated.
Figure 33. Effects of Unsynchronized OCR Latching in Up/Down Mode Compare Value changes Counter Value Compare Value PWM Output OCn Synchronized OCn Latch Compare Value changes Counter Value Compare Value PWM Output OCn Unsynchronized OCn Latch Glitch Figure 34. Effects of Unsynchronized OCR Latching in Overflow Mode.
ATmega161(L) In up/down PWM mode, the Timer Overflow Flag (TOV0 or TOV2) is set when the counter advances from $00. In overflow PWM mode, the Timer Overflow Flag is set as in normal Timer/Counter mode. Timer Overflow Interrupt0 and 2 operate exactly as in normal Timer/Counter mode, i.e., they are executed when TOV0 or TOV2 are set, provided that Timer Overflow Interrupt and global interrupts are enabled. This also applies to the Timer Output Compare flag and interrupt.
Asynchronous Operation of Timer/Counter2 When Timer/Counter2 operates asynchronously, some considerations must be taken: • Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the Timer Registers TCNT2, OCR2, and TCCR2 might get corrupted. A safe procedure for switching clock source is: 1. Disable the Timer/Counter2 interrupts by clearing OCIE2 and TOIE2. 2. Select clock source by setting AS2 as appropriate. 3. Write new values to TCNT2, OCR2, and TCCR2. 4.
ATmega161(L) Timer/Counter1 • Description of wake-up from Power-save mode when the timer is clocked asynchronously: When the interrupt condition is met, the wake-up process is started on the following cycle of the timer clock, that is, the timer is always advanced by at least 1 before the processor can read the counter value. The Interrupt Flags are updated three processor cycles after the processor clock has started.
clock period. The external clock signal is sampled on the rising edge of the internal CPU clock. The 16-bit Timer/Counter1 features both a high-resolution and a high-accuracy usage with the lower prescaling opportunities. Similarly, the high-prescaling opportunities make the Timer/Counter1 useful for lower speed functions or exact timing functions with infrequent actions.
ATmega161(L) • Bits 5, 4 – COM1B1, COM1B0: Compare Output Mode1B, Bits 1 and 0 The COM1B1 and COM1B0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1B (Output CompareB). This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. The following control configuration is given: Table 14.
• Bits 1..0 – PWM11, PWM10: Pulse Width Modulator Select Bits These bits select PWM operation of Timer/Counter1 as specified in Table 15. This mode is described on page 55. Table 15. PWM Mode Select Timer/Counter1 Control Register B – TCCR1B PWM11 PWM10 0 0 PWM operation of Timer/Counter1 is disabled. 0 1 Timer/Counter1 is an 8-bit PWM. 1 0 Timer/Counter1 is a 9-bit PWM. 1 1 Timer/Counter1 is a 10-bit PWM.
ATmega161(L) • Bits 2, 1, 0 – CS12, CS11, CS10: Clock Select1, Bits 2, 1 and 0 The Clock Select1 bits 2, 1 and 0 define the prescaling source of Timer/Counter1. Table 16. Clock 1 Prescale Select CS12 CS11 CS10 Description 0 0 0 Stop, the Timer/Counter1 is stopped. 0 0 1 CK 0 1 0 CK/8 0 1 1 CK/64 1 0 0 CK/256 1 0 1 CK/1024 1 1 0 External Pin T1, falling edge 1 1 1 External Pin T1, rising edge The Stop condition provides a Timer Enable/Disable function.
The Timer/Counter1 is realized as an up or up/down (in PWM mode) counter with read and write access. If Timer/Counter1 is written to and a clock source is selected, the Timer/Counter1 continues counting in the timer clock cycle after it is preset with the written value.
ATmega161(L) The Input Capture Register is a 16-bit read-only register. When the rising or falling edge (according to the Input Capture edge setting, ICES1) of the signal at the Input Capture pin (ICP) is detected, the current value of the Timer/Counter1 Register (TCNT1) is transferred to the Input Capture Register (ICR1). In the same cycle, the Input Capture Flag (ICF1) is set (one).
Table 18. Compare1 Mode Select in PWM Mode (1) CTC1 COM1X1 COM1X0 0 0 0 Not connected 0 0 1 Not connected 0 1 0 Cleared on compare match, up-counting. Set on compare match, down-counting (non-inverted PWM). 0 1 1 Cleared on compare match, down-counting. Set on compare match, up-counting (inverted PWM). 1 0 0 Not connected 1 0 1 Not connected 1 1 0 Cleared on compare match, set on overflow. 1 1 1 Set on compare match, cleared on overflow. Note: Effect on OCX1 1.
ATmega161(L) Figure 38. Effects of Unsynchronized OCR1 Latching in Overflow Mode1 PWM Output OC1x Synchronized OC1x Latch PWM Output OC1x Unsynchronized OC1x Latch Note: 1. Note: X = A or B During the time between the write and the latch operation, a read from OCR1A or OCR1B will read the contents of the temporary location. This means that the most recently written value always will read out of OCR1A/B.
Watchdog Timer The Watchdog Timer is clocked from a separate On-chip Oscillator that runs at 1 MHz. This is the typical value at VCC = 5V. See characterization data for typical values at other VCC levels. By controlling the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted (see Table 20 for a detailed description). The WDR (Watchdog Reset) instruction resets the Watchdog Timer. Eight different clock cycle periods can be selected to determine the reset period.
ATmega161(L) WDTOE bit is set (one). To disable an enabled Watchdog Timer, the following procedure must be followed: 1. In the same operation, write a logical “1” to WDTOE and WDE. A logical “1” must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical “0” to WDE. This disables the Watchdog. • Bits 2..
EEPROM Read/Write Access The EEPROM Access Registers are accessible in the I/O space. The write access time is in the range of 1.9 - 3.4 ms, depending on the frequency of the RC Oscillator used to time the EEPROM access time. See Table 22 for details. A selftiming function, however, lets the user software detect when the next byte can be written. If the user code contains code that writes the EEPROM, some precaution must be taken.
ATmega161(L) EEPROM Control Register – EECR Bit 7 6 5 4 3 2 1 0 $1C ($3C) – – – – EERIE EEMWE EEWE EERE Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 X 0 EECR • Bits 7..4 – Res: Reserved Bits These bits are reserved bits in the ATmega161 and will always read as zero. • Bit 3 – EERIE: EEPROM Ready Interrupt Enable When the I-bit in SREG and EERIE are set (one), the EEPROM Ready Interrupt is enabled. When cleared (zero), the interrupt is disabled.
bit. When EERE has been set, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEWE bit before starting the read operation. If a write operation is in progress when new data or address is written to the EEPROM I/O Registers, the write operation will be interrupted and the result is undefined. An RC Oscillator is used to time EEPROM write access. The table below lists the typical programming time listed for EEPROM access from CPU. Table 21.
ATmega161(L) Serial Peripheral Interface – SPI The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega161 and peripheral devices or between several AVR devices.
The interconnection between Master and Slave CPUs with SPI is shown in Figure 41. The PB7(SCK) pin is the Clock Output in the Master mode and is the clock input in the Slave mode. Writing to the SPI Data Register of the Master CPU starts the SPI clock generator, and the data written shifts out of the PB5(MOSI) pin and into the PB5(MOSI) pin of the Slave CPU. After shifting one byte, the SPI clock generator stops, setting the End-of-Transmission Flag (SPIF).
ATmega161(L) SS Pin Functionality When the SPI is configured as a Master (MSTR in SPCR is set), the user can determine the direction of the SS pin. If SS is configured as an output, the pin is a general output pin, which does not affect the SPI system. If SS is configured as an input, it must be held high to ensure Master SPI operation.
Figure 43. SPI Transfer Format with CPHA = 1 and DORD = 0 SPI Control Register – SPCR Bit 7 6 5 4 3 2 1 0 $0D ($2D) SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SPCR • Bit 7 – SPIE: SPI Interrupt Enable This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and if the global interrupt enable bit in SREG is set.
ATmega161(L) • Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0 These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on the Slave. The relationship between SCK and the Oscillator Clock frequency (fcl) is shown in Table 23: Table 23.
SPI Data Register – SPDR Bit 7 6 5 4 3 2 1 0 $0F ($2F) MSB LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value x x x x x x x x SPDR Undefined The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register. Writing to the register initiates data transmission. Reading the register causes the Shift Register Receive buffer to be read.
ATmega161(L) UARTs The ATmega161 features two full-duplex (separate Receive and Transmit Registers) Universal Asynchronous Receiver and Transmitters (UARTs).
• A new character has been written to UDRn before the stop bit from the previous character has been shifted out. The Shift Register is loaded when the stop bit of the character currently being transmitted has been shifted out. If the 10(11)-bit Transmit Shift Register is empty, data is transferred from UDRn to the Shift Register. At this time the UDREn (UART Data Register Empty) bit in the UART Control and Status Register, UCSRnA, is set.
ATmega161(L) Data Reception Figure 45 shows a block diagram of the UART Receiver. Figure 45.
Figure 46. Sampling Received Data(1) Note: 1. This figure is not valid when the UART speed is doubled. See “Double-speed Transmission” on page 78 for a detailed description. When the stop bit enters the Receiver, the majority of the three samples must be one to accept the stop bit. If two or more samples are logical “0”s, the Framing Error (FEn) Flag in the UART Control and Status Register (UCSRnA) is set.
ATmega161(L) Multi-processor Communication Mode The Multi-processor Communication mode enables several Slave MCUs to receive data from a master MCU. This is done by first decoding an address byte to find out which MCU has been addressed. If a particular Slave MCU has been addressed, it will receive the following data bytes as normal, while the other Slave MCUs will ignore the data bytes until another address byte is received.
UART1 Control and Status Registers – UCSR1A Bit 7 6 5 4 3 2 1 0 RXC1 TXC1 UDRE1 FE1 OR1 – U2X1 MPCM1 Read/Write R R/W R R R R R/W R/W Initial Value 0 0 1 0 0 0 0 0 $02 ($22) UCSR1A • Bit 7 – RXC0/RXC1: UART Receive Complete This bit is set (one) when a received character is transferred from the Receiver Shift Register to UDRn. The bit is set regardless of any detected framing errors.
ATmega161(L) • Bit 2 – Res: Reserved Bit This bit is reserved bit in the ATmega161 and will always read as zero. • Bit 1 – U2X0/U2X1: Double the UART Transmission Speed When this bit is set (one), the UART speed will be doubled. This means that a bit will be transmitted/received in 8 CPU clock periods instead of 16 CPU clock periods. For a detailed description, see “Double-speed Transmission” on page 78.
• Bit 2 – CHR90/CHR91: 9-bit Characters When this bit is set (one), transmitted and received characters are nine bits long, plus start and stop bits. The ninth bit is read and written by using the RXB8n and TXB8 bits in UCSRnB, respectively. The ninth data bit can be used as an extra stop bit or a parity bit. • Bit 1 – RXB80/RXB81: Receive Data Bit 8 When CHR9n is set (one), RXB8n is the ninth data bit of the received character.
ATmega161(L) Table 24. UBR Settings at Various Crystal Frequencies Baud Rate 1 MHz %Error 1.8432 MHz %Error 2 MHz %Error 2.4576 MHz %Error 2400 UBR= 25 0.2 UBR= 47 0.0 UBR= 51 0.2 UBR= 63 0.0 4800 UBR= 12 0.2 UBR= 23 0.0 UBR= 25 0.2 UBR= 31 0.0 6 7.5 UBR= 9600 UBR= 11 0.0 UBR= 12 0.2 UBR= 15 0.0 3 7.8 UBR= 8 3.7 UBR= 10 3.1 14400 UBR= 7 0.0 UBR= 2 7.8 UBR= 6 7.5 UBR= 19200 UBR= 5 0.0 UBR= 7 0.0 1 7.8 UBR= 3 7.8 UBR= 4 6.3 28800 UBR= 3 0.0 UBR= 1 22.9 UBR= 2 7.8 UBR= 38400 UBR= 2 0.0 UBR= 3 0.0 0 7.
UART0 and UART1 High Byte Baud Rate Register UBRRHI Bit $20 ($40) 7 6 5 MSB1 4 3 LSB1 MSB0 2 1 0 LSB0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 UBRRHI The UART Baud Register is a 12-bit register. The four most significant bits are located in a separate register, UBRRHI. Note that both UART0 and UART1 share this register. Bit 7 to bit 4 of UBRRHI contain the four most significant bits of the UART1 Baud Register.
ATmega161(L) The Baud Rate Generator in Double UART Speed Mode Note that the baud rate equation is different from the equation on page 76 when the UART speed is doubled: f CK BAUD = ----------------------------8(UBR + 1 ) • BAUD = Baud rate • fCK= Crystal Clock frequency • UBR = Contents of the UBRRHI and UBRR Registers (0 - 4095) • Note that this equation is only valid when the UART transmission speed is doubled.
Table 25. UBR Settings at Various Crystal Frequencies in Double-speed Mode Baud Rate 1.0000 MHz % Error 1.8432 MHz % Error 2.0000 MHz % Error 2400 4800 9600 14400 19200 28800 38400 57600 76800 115200 230400 UBR = 51 UBR = 25 UBR = 12 UBR = 8 UBR = 6 UBR = 3 UBR = 2 UBR = 1 UBR = 1 UBR = 0 - 0.2 0.2 0.2 3.7 7.5 7.8 7.8 7.8 22.9 84.3 - UBR = 95 UBR = 47 UBR = 23 UBR = 15 UBR = 11 UBR = 7 UBR = 5 UBR = 3 UBR = 2 UBR = 1 UBR = 0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.
ATmega161(L) Analog Comparator The Analog Comparator compares the input values on the positive input PB2 (AIN0) and negative input PB3 (AIN1). When the voltage on the positive input PB2 (AIN0) is higher than the voltage on the negative input PB3 (AIN1), the Analog Comparator Output (ACO) is set (one). The comparator’s output can be set to trigger the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate interrupt, exclusive to the Analog Comparator.
• Bit 4 – ACI: Analog Comparator Interrupt Flag This bit is set (one) when a comparator output event triggers the interrupt mode defined by ACI1 and ACI0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set (one) and the I-bit in SREG is set (one). ACI is cleared by hardware when executing the corresponding Interrupt Handling Vector. Alternatively, ACI is cleared by writing a logical “1” to the Flag.
ATmega161(L) Internal Voltage Reference ATmega161 features an internal voltage reference with a nominal voltage of 1.22V. This reference can be used as an input to the Analog Comparator. Voltage Reference The voltage reference has a start-up time that may have an influence on the way it Enable Signals and Start- should be used. The maximum start-up time is TBD. To save power, the reference is on only when the AINBG bit in ACSR is set.
Interface to External Memory MCU Control Register – MCUCR Extended MCU Control Register – EMCUCR With all the features the external memory interface provides, it is well suited to operate as an interface to memory devices such as external SRAM and Flash, and peripherals such as LCD display, A/D, D/A, etc. The control bits for the external memory interface are located in two registers, the MCU Control Register (MCUCR) and the Extended MCU Control Register (EMCUCR).
ATmega161(L) • Bits 3..2 EMCUCR – SRW01, SRW00: Wait State Select Bits for Lower Page The SRW01 and SRW00 bits control the number of wait states for the lower page of the external memory address space (see Table 27). Table 27. Wait States(1) SRWn1 SRWn0 0 0 No wait states 0 1 Wait one cycle during read/write strobe 1 0 Wait two cycles during read/write strobe 1 1 Wait two cycles during read/write and wait one cycle before driving out new address Note: Wait States 1.
Figure 49. External Memory with Page Select Data Memory $0000 Internal memory $0460 Lower page SRW01 SRW00 SRL[2..0] External Memory (0-63K x 8) Upper page SRW11 SRW10 $FFFF Figure 50. External Data Memory Cycles without Wait State (SRWn1 = 0 and SRWn0 =0)(1) T1 T2 T3 T4 System Clock Ø Prev. addr. XX Data/Address [7..0] Prev. data XX Address Prev. data XX Address XX Address XX Data XX Write Address [15..8] Data XX Read ALE WR Data/Address [7..0] RD Note: 86 1.
ATmega161(L) Figure 51. External Data Memory Cycles with SRWn1 = 0 and SRWn0 = 1(1) T1 T2 T4 T3 T5 System Clock Ø Prev. addr. XX Data/Address [7..0] Prev. data XX Address Prev. data XX Address XX Address XX Data XX Write Address [15..8] Data XX Read ALE WR Data/Address [7..0] RD Note: 1. SRWn1 = SRW11 (upper page) or SRW01 (lower page), SRWn0 = SRW10 (upper page) or SRW00 (lower page).
Using the External Memory Interface The interface consists of: Port A: multiplexed low-order address bus and data bus Port C: high-order address bus The ALE pin: address latch enable The RD and WR pin: read and write strobes The external memory interface is enabled by setting the external SRAM enable bit (SRE) of the MCU Control Register (MCUCR) and will override the setting of the Data Direction Registers DDRA, DDRD and DDRE.
ATmega161(L) I/O Ports All AVR ports have true read-modify-write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies for changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input). Port A Port A is an 8-bit bi-directional I/O port.
Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Table 29. DDAn Effects on Port A Pins(1) DDAn PORTAn I/O Pull-up 0 0 Input No Tri-state (high-Z) 0 1 Input Yes PAn will source current if ext. pulled low. 1 0 Output No Push-pull Zero Output 1 1 Output No Push-pull One Output Note: Port A Schematics Comment 1. n: 7,6…0, pin number Note that all port pins are synchronized.
ATmega161(L) Port B Port B is an 8-bit bi-directional I/O port. Three I/O memory address locations are allocated for the Port B, one each for the Data Register – PORTB, $18($38), Data Direction Register – DDRB, $17($37) and the Port B Input Pins – PINB, $16($36). The Port B Input Pins address is read-only, while the Data Register and the Data Direction Register are read/write. All port pins have individually selectable pull-up resistors.
Port B as General Digital I/O All eight pins in Port B have equal functionality when used as digital I/O pins. PBn, general I/O pin: The DDBn bit in the DDRB Register selects the direction of this pin. If DDBn is set (one), PBn is configured as an output pin. If DDBn is cleared (zero), PBn is configured as an input pin. If PORTBn is set (one) when the pin is configured as an input pin, the MOS pull-up resistor is activated.
ATmega161(L) • TXD1/AIN1 – Port B, Bit 3 AIN1, Analog Comparator Negative Input. This pin also serves as the negative input of the On-chip Analog Comparator. TXD1, Transmit Data (Data output pin for the UART1). When the UART1 Transmitter is enabled, this pin is configured as an output regardless of the value of DDRB3. • RXD1/AIN0 – Port B, Bit 2 AIN0, Analog Comparator Positive Input. This pin also serves as the positive input of the On-chip Analog Comparator.
Port B Schematics Note that all port pins are synchronized. The synchronization latches are, however, not shown in the figures. Figure 56. Port B Schematic Diagram (Pins PB0 and PB1) DDBn PBn PORTBn COMx0 COMx1 WP: WRITE PORTB WD: WRITE DDRB RL: READ PORTB LATCH RP: READ PORTB PIN RD: READ DDRB n: 0,1 x: 0,2 COMP.
ATmega161(L) Figure 57. Port B Schematic Diagram (Pin PB2) RD MOS PULLUP RESET Q D DDB2 C DATA BUS WD RESET Q D PORTB2 C PB2 RL WP RP RXEN1 RXD1 WP: WD: RL: RP: RD: RXD1: RXEN1: AIN0: WRITE PORTB WRITE DDRB READ PORTB LATCH READ PORTB PIN READ DDRB UART1 RECEIVE DATA UART1 RECEIVE ENABLE ANALOG COMPARATOR POSITIVE INPUT AIN0 Figure 58.
Figure 59. Port B Schematic Diagram (Pin PB4) RD MOS PULLUP RESET Q D DDB4 C DATA BUS WD RESET Q D PORTB4 C PB4 RL WP RP WP: WD: RL: RP: RD: MSTR: SPE: MSTR SPE WRITE PORTB WRITE DDRB READ PORTB LATCH READ PORTB PIN READ DDRB SPI MASTER ENABLE SPI ENABLE SPI SS Figure 60.
ATmega161(L) Figure 61. Port B Schematic Diagram (Pin PB6) RD MOS PULLUP RESET R Q D DDB6 WD RESET R Q D PORTB6 PB6 DATA BUS C C RL WP RP WP: WD: RL: RP: RD: SPE: MSTR WRITE PORTB WRITE DDRB READ PORTB LATCH READ PORTB PIN READ DDRB SPI ENABLE MASTER SELECT MSTR SPE SPI SLAVE OUT SPI MASTER IN Figure 62.
Port C Port C is an 8-bit bi-directional I/O port. Three I/O memory address locations are allocated for the Port C, one each for the Data Register – PORTC, $15($35), Data Direction Register – DDRC, $14($34) and the Port C Input Pins – PINC, $13($33). The Port C Input Pins address is read-only, while the Data Register and the Data Direction Register are read/write. All port pins have individually selectable pull-up resistors. The Port C output buffers can sink 20 mA and thus drive LED displays directly.
ATmega161(L) Table 32. DDCn Effects on Port C Pins(1) DDCn PORTCn I/O Pull-up 0 0 Input No Tri-state (high-Z) 0 1 Input Yes PCn will source current if ext. pulled low 1 0 Output No Push-pull Zero Output 1 1 Output No Push-pull One Output Note: Port C Schematics Comment 1. n: 7, 6,…0, pin number Note that all port pins are synchronized. The synchronization latch is, however, not shown in the figure. Figure 63.
Port D Port D is an 8-bit bi-directional I/O port with internal pull-up resistors. Three I/O address locations are allocated for the Port D, one each for the Data Register – PORTD, $12($32), Data Direction Register – DDRD, $11($31) and the Port D Input Pins – PIND, $10($30). The Port D Input Pins address is read-only, while the Data Register and the Data Direction Register are read/write. The Port D output buffers can sink 20 mA.
ATmega161(L) has to be cleared (zero) or the pin has to be configured as an output pin. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Table 34. DDDn Bits on Port D Pins(1) DDDn PORTDn I/O Pull-up 0 0 Input No Tri-state (high-Z) 0 1 Input Yes PDn will source current if ext. pulled low. 1 0 Output No Push-pull Zero Output 1 1 Output No Push-pull One Output Notes: Alternate Functions of Port D Comment 1.
Port D Schematics Note that all port pins are synchronized. The synchronization latches are, however, not shown in the figures. Figure 64. Port D Schematic Diagram (Pin PD0) RD MOS PULLUP RESET Q D DDD0 C DATA BUS WD RESET Q D PORTD0 C PD0 RL WP RP WP: WD: RL: RP: RD: RXD0: RXEN0: RXEN0 WRITE PORTD WRITE DDRD READ PORTD LATCH READ PORTD PIN READ DDRD UART0 RECEIVE DATA UART0 RECEIVE ENABLE RXD0 Figure 65.
ATmega161(L) Figure 66. Port D Schematic Diagram (Pins PD2 and PD3) WP: WD: RL: RP: RD: n: m: WRITE PORTD WRITE DDRD READ PORTD LATCH READ PORTD PIN READ DDRD 2, 3 0, 1 Figure 67.
Figure 68. Port D Schematic Diagram (Pin PD5) COMP. MATCH 1A PWM10 PWM11 FOC1A WP: WD: RL: RP: RD: AS2 WRITE PORTD WRITE DDRD READ PORTD LATCH READ PORTD PIN READ DDRD ASYNCH SELECT T/C2 Figure 69.
ATmega161(L) Figure 70.
Port E Port E is a 3-bit bi-directional I/O port with internal pull-up resistors. Three I/O address locations are allocated for the Port E, one each for the Data Register – PORTE, $07($27), Data Direction Register – DDRE, $06($26) and the Port E Input Pins – PINE, $05($25). The Port E Input Pins address is read-only, while the Data Register and the Data Direction Register are read/write. The Port E output buffers can sink 20 mA.
ATmega161(L) Table 36. DDEn Bits on Port E Pins(1) DDEn PORTEn I/O Pull-up 0 0 Input No Tri-state (high-Z) 0 1 Input Yes PEn will source current if ext. pulled low. 1 0 Output No Push-pull Zero Output 1 1 Output No Push-pull One Output Note: Alternate Functions of Port E Comment 1. n: 2,1,0, pin number.
Port E Schematics Figure 71. Port E Schematic Diagram (Pin PE0) RD MOS PULLUP RESET Q R D DDE0 C DATA BUS WD RESET R Q D PORTE0 PE0 C RL WP RP WP: WD: RL: RP: RD: ACIC: ACO: WRITE PORTE WRITE DDRE READ PORTE LATCH READ PORTE PIN READ DDRE COMPARATOR IC ENABLE COMPARATOR OUTPUT 0 NOISE CANCELER EDGE SELECT ICNC1 ICES1 ICF1 1 ACIC ACO '1' INT2 Q D PORTE0 C R HW CLEAR SW CLEAR ISC2 Figure 72.
ATmega161(L) Figure 73. Port E Schematic Diagram (Pin PE2) DDE2 PE2 PORTE2 WP: WD: RL: RP: RD: WRITE PORTE WRITE DDRE READ PORTE LATCH READ PORTE PIN READ DDRE COM1B0 COM1B1 COMP.
Memory Programming Boot Loader Support The ATmega161 provides a mechanism for downloading and uploading program code by the MCU itself. This feature allows flexible application software updates, controlled by the MCU using a Flash-resident Boot Loader program. The ATmega161 Flash memory is organized in two main sections: 1. The Application Code section (address $0000 - $1DFF) 2. The Boot Loader section/Boot block (address $1E00 - $1FFF) Figure 74.
ATmega161(L) • Protect the entire Flash from a software update by the Boot Loader program • Only protect the Boot Loader section from a software update by the Boot Loader program • Only protect the Application Code section from a software update by the Boot Loader program • Allow software update in the entire Flash See Table 37 and Table 38 for further details. The Boot Lock bits can be set in software and in Serial or Parallel Programming mode, but they can only be cleared by a Chip Erase command.
Table 39. Boot Reset Fuse, BOOTRST(1) BOOTRST Note: Reset Address 1 Reset Vector = Application Reset (address $0000) 0 Reset Vector = Boot Loader Reset (address $1E00) 1. “1” means unprogrammed, “0” means programmed Capabilities of the Boot Loader The program code within the Boot Loader section has the ability to read from and write into the entire Flash, including the Boot Loader Memory.
ATmega161(L) Fill the Temporary Buffer To write an instruction word, set up the address in the Z-pointer and data in R1:R0, write “0001” to SPMCR, and execute SPM within four clock cycles after writing SPMCR. The content of Z6:Z1 is used to address the data in the temporary buffer. Z13:Z7 must point to the page that is supposed to be written.
Store Program Memory Control Register – SPMCR The Store Program Memory Control Register contains the control bits needed to control the programming of the Flash from internal code execution. Bit 7 6 $37 ($57) – – 5 Read/Write R R R Initial Value 0 0 0 4 3 2 1 0 BLBSET PGWRT PGERS SPMEN R R/W R/W R/W R/W 0 0 0 0 0 SPMCR • Bits 7..4 – Res: Reserved Bits These bits are reserved bits in the ATmega161 and always read as zero.
ATmega161(L) EEPROM Write Prevents Writing to SPMCR Note that an EEPROM write operation will block all software programming to Flash. Reading the Fuse and Lock bits from software will also be prevented during the EEPROM write operation. It is recommended that the user check the status bit (EEWE) in the EECR Register and verify that the bit is cleared before writing to the SPMCR Register. Reading the Fuse and Lock bits from Software It is possible to read both the Fuse and Lock bits from software.
Program Memory Lock bits The ATmega161 MCU provides six Lock bits that can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 40. The Lock bits can only be erased to “1” with the Chip Erase command. Table 40. Lock Bit Protection Modes (1) Memory Lock bits LB Mode LB1 LB2 1 1 1 No memory lock features enabled 2 0 1 Further programming of the Flash and EEPROM is disabled in parallel and Serial Programming modes.
ATmega161(L) • CKSEL2..0: See Table 4, “Reset Delay Selections(3),” on page 26, for which combination of CKSEL2..0 to use. Default value is “010”. The status of the Fuse bits is not affected by Chip Erase. Note that the Fuse bits are locked if Lock bit1 (LB1) or Lock bit2 (LB2) is programmed. Program the Fuse bits before programming the Lock bits. Signature Bytes All Atmel microcontrollers have a 3-byte signature code that identifies the device. This code can be read in both Serial and Parallel modes.
Parallel Programming This section describes how to parallel program and verify Flash Program memory, EEPROM Data memory, Lock bits and Fuse bits in the ATmega161. Pulses are assumed to be at least 500 ns unless otherwise noted. Signal Names In this section, some pins of the ATmega161 are referenced by signal names describing their functionality during parallel programming (see Figure 75 and Table 42). Pins not described in the following table are referenced by pin name.
ATmega161(L) Table 42. Pin Name Mapping Signal Name in Programming Mode Pin Name I/O PAGEL PD7 I Program Memory Page Load BS2 PA0 I Byte Select 2 (Always low) DATA PB7 - 0 I/O Function Bi-directional Data Bus (Output when OE is low) Table 43.
Programming the Flash The Flash is organized as 128 pages of 128 bytes each. When programming the Flash, the program data is latched into a page buffer. This allows one page of program data to be programmed simultaneously. The following procedure describes how to program the entire Flash memory: A. Load Command “Write Flash” 1. Set XA1, XA0 to “10”. This enables command loading. 2. Set BS1 to “0”. 3. Set DATA to “0001 0000”. This is the command for Write Flash. 4. Give XTAL1 a positive pulse.
ATmega161(L) 1. Give WR a negative pulse. This starts programming of the entire page of data. RDY/BSYgoes low. 2. Wait until RDY/BSY goes high. (See Figure 77 for signal waveforms.) J. End Page Programming 1. Set XA1, XA0 to “10”. This enables command loading. 2. Set DATA to “0000 0000”. This is the command for No Operation. 3. Give XTAL1 a positive pulse. This loads the command, and the internal write signals are reset. K. Repeat “A” through “J” 128 times or until all data have been programmed. Figure 76.
Programming the EEPROM The programming algorithm for the EEPROM Data memory is as follows (refer to “Programming the Flash” for details on command, address and data loading): 1. A: Load Command “0001 0001”. 2. H: Load Address High Byte ($00 - $01) 3. B: Load Address Low Byte ($00 - $FF) 4. E: Load Data Low Byte ($00 - $FF) L: Write Data Low Byte 1. Set BS to “0”. This selects low data. 2. Give WR a negative pulse. This starts programming of the data byte. RDY/BSY goes low. 3.
ATmega161(L) Reading the Flash The algorithm for reading the Flash memory is as follows (refer to “Programming the Flash” on page 120 for details on command and address loading): 1. A: Load Command “0000 0010”. 2. H: Load Address High Byte ($00 - $1F) 3. B: Load Address Low Byte ($00 - $FF) 4. Set OE to “0”, and BS1 to “0”. The Flash word Low byte can now be read at DATA. 5. Set BS to “1”. The Flash word High byte can now be read at DATA. 6. Set OE to “1”.
Reading the Fuse and Lock Bits The algorithm for reading the Fuse and Lock bits is as follows (refer to “Programming the Flash” on page 120 for details on command loading): 1. A: Load Command “0000 0100”. 2. Set OE to “0”, and BS to “0”. The status of the Fuse bits can now be read at DATA (“0” means programmed). Bit 6 = BOOTRST Fuse bit Bit 5 = SPIEN Fuse bit Bit 4 = SUT Fuse bit Bit 3 = “1”. This bit is reserved and must be left unprogrammed (“1”). Bits 2 - 0 = CKSEL2..0 Fuse bits 3.
ATmega161(L) Table 45. Parallel Programming Characteristics, TA = 25°C ± 10%, V CC = 5V ± 10%(1)(2)(3) Symbol Parameter Min VPP Programming Enable Voltage 11.
Serial Programming Algorithm When writing serial data to the ATmega161, data is clocked on the rising edge of SCK. When reading data from the ATmega161, data is clocked on the falling edge of SCK. See Figure 80, Figure 81 and Table 49 for timing details. To program and verify the ATmega161 in the Serial Programming mode, the following sequence is recommended (see 4-byte instruction formats in Table 48): 1. Power-up sequence: Apply power between VCC and GND while RESET and SCK are set to “0”.
ATmega161(L) tWD_FLASH before programming the next page. As a chip-erased device contains $FF in all locations, programming of addresses that are meant to contain $FF can be skipped. See Table 46 for tWD_FLASH value. Data Polling EEPROM When a new byte has been written and is being programmed into EEPROM, reading the address location being programmed will give the value $FF. At the time the device is ready for a new byte, the programmed value will read correctly.
. Table 48. Serial Programming Instruction Set(1) Instruction Format Instruction Byte 1 Byte 2 Byte 3 Byte 4 Programming Enable 1010 1100 0101 0011 xxxx xxxx xxxx xxxx Enable Serial Programming after RESET goes low. Chip Erase 1010 1100 100x xxxx xxxx xxxx xxxx xxxx Chip Erase EEPROM and Flash. Read Program Memory 0010 H000 xxxa aaaa bbbb bbbb oooo oooo Read H (high or low) data o from Program memory at word address a:b.
ATmega161(L) Serial Programming Characteristics Figure 81. Serial Programming Timing MOSI SCK tSLSH tSHOX tOVSH tSHSL MISO tSLIV Table 49. Serial Programming Characteristics, TA = -40°C to 85°C, V CC = 2.7 - 5.5V (unless otherwise noted) Symbol Parameter 1/tCLCL Oscillator Frequency tCLCL Oscillator Period Min Typ Max Units (VCC = 2.7 - 5.5V) 0 4 MHz (VCC = 4.0 - 5.5V) 0 8 MHz (VCC = 2.7 - 5.5V) 250 ns (VCC = 4.0 - 5.
Electrical Characteristics Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C Storage Temperature ..................................... -65°C to +150°C Voltage on Any Pin except RESET with Respect to Ground .............................-1.0V to VCC + 0.5V Voltage on RESET with Respect to Ground ....-1.0V to +13.0V *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
ATmega161(L) DC Characteristics TA = -40°C to 85°C, VCC = 2.7V to 5.5V (unless otherwise noted)(1)(2)(3)(4)(5) Symbol VIL Parameter Condition Input Low Voltage (Except XTAL1) VIL1 Input Low Voltage (XTAL1) VIH Input High Voltage (Except XTAL1, RESET) VIH1 VIH2 Input High Voltage (XTAL1) Input High Voltage (RESET) (3) Min Typ Max Units 0.3 VCC (1) V 0.2 VCC (1) V 0.6 VCC(2) VCC + 0.5 V 0.8 VCC (2) VCC + 0.5 V 0.9 VCC (2) VCC + 0.5 V 0.6 0.5 V V -0.5 -0.
If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current greater than the listed test condition. 5. Minimum VCC for power-down is 2V. External Clock Drive Waveforms Figure 82. External Clock VIH1 VIL1 Table 50. External Clock Drive(1) VCC = 2.7V to 5.
ATmega161(L) External Data Memory Timing Table 51. External Data Memory Characteristics, 4.0 - 5.5 Volts, No Wait State 8 MHz Oscillator Symbol Parameter 0 1/tCLCL Oscillator Frequency 1 tLHLL ALE Pulse Width 2 tAVLL 3a Min Variable Oscillator Max Min Max Unit 0.0 8.0 MHz 95 1.0tCLCL-30 ns Address Valid A to ALE Low 22.5 0.
Table 53. External Data Memory Characteristics, 4.0 - 5.5 Volts, SRWn1 = 1, SRWn0 = 0 8 MHz Oscillator Min Max Variable Oscillator Symbol Parameter Min Max Unit 0 1/tCLCL Oscillator Frequency 0.0 8.0 MHz 10 tRLDV Read Low to Data Valid 12 tRLRH RD Pulse Width 355 3.0tCLCL-20 ns 15 tDVWH Data Valid to WR High 345 3.0tCLCL-30 ns 16 tWLWH WR Pulse Width 35 3.0tCLCL-20 ns 310 3.0tCLCL-65 ns Table 54. External Data Memory Characteristics, 4.0 - 5.
ATmega161(L) Table 55. External Data Memory Characteristics, 2.7 - 5.5 Volts, No Wait State (Continued) 4 MHz Oscillator Max Variable Oscillator Symbol Parameter Min Min Max 12 tRLRH RD Pulse Width 230 1.0tCLCL-20 ns 13 tDVWL Data Setup to WR Low 70 0.5tCLCL-55 ns 14 tWHDX Data Hold After WR High 125 0.5tCLCL-0 ns 15 tDVWH Data Valid to WR High 210 1.0tCLCL-40 ns 16 tWLWH WR Pulse Width 230 1.0tCLCL-20 Notes: 1. This assumes 50% clock duty cycle.
Figure 83. External Memory Timing (SRWn1 = 0, SRWn0 = 0) T1 T2 T4 T3 System Clock Ø 1 ALE 4 Address [15..8] Prev. addr. 7 XX Address 15 2 Data/Address [7..0] Prev. data 3a 13 Address XX XX Data XX 6 Write 14 16 WR 3b Prev. data XX XX 10 8 Read Data/Address [7..0] 11 9 Data Address 5 12 RD Figure 84. External Memory Timing (SRWn1 = 0, SRWn0 = 1) T1 T2 T3 T4 T5 System Clock Ø 1 ALE 4 Address [15..8] Prev. addr. 7 XX Address XX 15 2 Data/Address [7..0] Prev.
ATmega161(L) Figure 85. External Memory Timing (SRWn1 = 1, SRWn0 = 0) T1 T2 T4 T3 T5 T6 System Clock Ø 1 ALE 4 Address [15..8] Prev. addr. 7 XX Address XX 15 2 Data/Address [7..0] Prev. data 3a 13 Address XX Data XX 6 Write 14 16 WR 3b Prev. data 11 9 Data Address 5 XX XX 10 8 Read Data/Address [7..0] 12 RD Figure 86. External Memory Timing (SRWn1 = 1, SRWn0 = 1)(1) T1 T2 T3 T4 T6 T5 T7 System Clock Ø 1 ALE 4 Address [15..8] Prev. addr.
Typical Characteristics Analog Comparator offset voltage is measured as absolute offset. Figure 87. Analog Comparator Offset Voltage vs. Common Mode Voltage ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE VCC = 5V 18 16 TA = 25˚C OFFSET VOLTAGE (mV) 14 12 TA = 85˚C 10 8 6 4 2 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 COMMON MODE VOLTAGE (V) Figure 88. Analog Comparator Offset Voltage vs. Common Mode Voltage ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE VCC = 2.
ATmega161(L) Figure 89. Analog Comparator Input Leakage Current ANALOG COMPARATOR INPUT LEAKAGE CURRENT VCC = 6V TA = 25˚C 60 50 IACLK (nA) 40 30 20 10 0 -10 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 VIN (V) Figure 90. Watchdog Oscillator Frequency vs. VCC WATCHDOG OSCILLATOR FREQUENCY vs. VCC 1600 TA = 25˚C 1400 TA = 85˚C FRC (kHz) 1200 1000 800 600 400 200 0 2 2.5 3 3.5 4 4.5 5 5.5 6 VCC (V) Sink and source capabilities of I/O ports are measured on one pin at a time.
Figure 91. Pull-up Resistor Current vs. Input Voltage PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE VCC = 5V 120 TA = 25˚C 100 TA = 85˚C IOP (µA) 80 60 40 20 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VOP (V) Figure 92. Pull-up Resistor Current vs. Input Voltage PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE VCC = 2.7V 30 TA = 25˚C 25 TA = 85˚C IOP (µA) 20 15 10 5 0 0 0.5 1 1.5 2 2.
ATmega161(L) Figure 93. I/O Pin Sink Current vs. Output Voltage I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE VCC = 5V 70 TA = 25˚C 60 TA = 85˚C IOL (mA) 50 40 30 20 10 0 0 0.5 1 1.5 2 2.5 3 VOL (V) Figure 94. I/O Pin Source Current vs. Output Voltage I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE VCC = 5V 20 TA = 25˚C 18 16 TA = 85˚C IOH (mA) 14 12 10 8 6 4 2 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.
Figure 95. I/O Pin Sink Current vs. Output Voltage I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE VCC = 2.7V 25 TA = 25˚C 20 IOL (mA) TA = 85˚C 15 10 5 0 0 0.5 1 1.5 2 VOL (V) Figure 96. I/O Pin Source Current vs. Output Voltage I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE VCC = 2.7V 6 TA = 25˚C 5 TA = 85˚C IOH (mA) 4 3 2 1 0 0 0.5 1 1.5 2 2.
ATmega161(L) Figure 97. I/O Pin Input Threshold vs. VCC I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC TA = 25˚C THRESHOLD VOLTAGE (V) 2.5 2 1.5 1 0.5 0 2.7 4.0 5.0 VCC Figure 98. I/O Pin Input Hysteresis vs. VCC I/O PIN INPUT HYSTERESIS vs. VCC TA = 25˚C 0.18 0.16 IINPUT HYSTERESIS (V) 0.14 0.12 0.1 0.08 0.06 0.04 0.02 0 2.7 4.0 5.
Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page $3F ($5F) SREG I T H S V N Z C page 21 $3E ($5E) SPH SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 page 22 $3D ($5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 page 22 $3C ($5C) SPL Reserved $3B ($5B) GIMSK INT1 INT0 INT2 - - - - - page 30 $3A ($5A) GIFR INTF1 INTF0 INTF2 $39 ($59) TIMSK TOIE1 OCIE1A OCIE1B TOIE2 TICIE1 OCIE2 TOIE0 OCIE0 page 31 $38 ($58) TIFR TOV1 OCF1A
ATmega161(L) Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. Some of the Status Flags are cleared by writing a logical “1” to them. Note that the CBI and SBI instructions will operate on all bits in the I/O Register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers $00 to $1F only.
Instruction Set Summary Mnemonic Operands Description Operation Flags # Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add Two Registers Rd ← Rd + Rr Z,C,N,V,H 1 ADC Rd, Rr Add with Carry Two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1 ADIW Rdl, K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 2 SUB Rd, Rr Subtract Two Registers Rd ← Rd - Rr Z,C,N,V,H 1 SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1 SBC Rd, Rr Subtract with Carry Two Registers
ATmega161(L) Instruction Set Summary (Continued) Mnemonic Operands Description Operation Flags BRTS k Branch if T-flag Set if (T = 1) then PC ← PC + k + 1 None # Clocks 1/2 BRTC k Branch if T-flag Cleared if (T = 0) then PC ← PC + k + 1 None 1/2 BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1 None 1/2 BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None 1/2 BRIE k Branch if Interrupt Enabled if (I = 1) then PC ← PC + k + 1 None
Instruction Set Summary (Continued) Mnemonic Description Operation Flags SEZ Operands Set Zero Flag Z←1 Z # Clocks 1 CLZ Clear Zero Flag Z←0 Z 1 SEI Global Interrupt Enable I←1 I 1 CLI Global Interrupt Disable I←0 I 1 1 SES Set Signed Test Flag S←1 S CLS Clear Signed Test Flag S←0 S 1 SEV Set Two’s Complement Overflow V←1 V 1 CLV Clear Two’s Complement Overflow V←0 V 1 SET Set T in SREG T←1 T 1 CLT Clear T in SREG T←0 T 1 SEH Set Half-carry Flag in SREG
ATmega161(L) Ordering Information Speed (MHz) Power Supply 4 2.7 - 5.5V 8 Note: 4.0 - 5.5V Ordering Code Package Operation Range ATmega161-4AC ATmega161-4PC 44A 40P6 Commercial (0°C to 70°C) ATmega161-4AI ATmega161-4PI 44A 40P6 Industrial (-40°C to 85°C) ATmega161-8AC ATmega161-8PC 44A 40P6 Commercial (0°C to 70°C) ATmega161-8AI ATmega161-8PI 44A 40P6 Industrial (-40°C to 85°C) This device can also be supplied in wafer form.
Packaging Information 44A 44-lead, Thin (1.0mm) Plastic Quad Flat Package (TQFP), 10x10mm body, 2.0mm footprint, 0.8mm pitch. Dimension in Millimeters and (Inches)* JEDEC STANDARD MS-026 ACB 12.25(0.482) SQ 11.75(0.462) PIN 1 ID PIN 1 0.45(0.018) 0.30(0.012) 0.80(0.0315) BSC 10.10(0.394) SQ 9.90(0.386) 1.20(0.047) MAX 0.20(0.008) 0.09(0.004) 0˚~7˚ 0.75(0.030) 0.45(0.018) 0.15(0.006) 0.05(0.002) *Controlling dimension: millimetter REV.
ATmega161(L) 40P6 40-lead, Plastic Dual Inline Parkage (PDIP), 0.600" wide Demension in Millimeters and (Inches)* JEDEC STANDARD MS-011 AC 52.71(2.075) 51.94(2.045) PIN 1 13.97(0.550) 13.46(0.530) 48.26(1.900) REF 4.83(0.190)MAX SEATING PLANE 0.38(0.015)MIN 3.56(0.140) 3.05(0.120) 2.54(0.100)BSC 1.65(0.065) 1.27(0.050) 0.56(0.022) 0.38(0.015) 15.88(0.625) 15.24(0.600) 0º ~ 15º REF 0.38(0.015) 0.20(0.008) 17.78(0.700)MAX *Controlling dimension: Inches REV.
Errata ATmega161 Rev. E • • • • • PWM not Phase Correct Increased Interrupt Latency Interrupt Return Fails when Stack Pointer Addresses the External Memory Writing UBBRH Affects both UART0 and UART1 Store Program Memory Instruction May Fail 5. PWM not Phase Correct In phase correct PWM mode, a change from OCRx = TOP to anything less than TOP does not change the OCx output. This gives a phase error in the following period. Problem Fix/Workaround Make sure this issue is not harmful to the application. 4.
ATmega161(L) 1. Store Program Memory Instruction May Fail At certain frequencies and voltages, the store program memory (SPM) instruction may fail. Problem Fix/Workaround Avoid using the SPM instruction.
Data Sheet Change Log for ATmega161 This document contains a log on the changes made to the data sheet for ATmega161. Changes from Rev. 1228B-09/01 to Rev. 1228C-08/02 All page numbers refers to this document. 154 1 Description of Brown-out Detector (BOD) removed from data sheet.
ATmega161(L) Table of Contents Features................................................................................................. 1 Disclaimer.............................................................................................. 1 Pin Configuration.................................................................................. 2 Description ............................................................................................ 3 Block Diagram ..........................................
Internal Voltage Reference ................................................................ 83 Voltage Reference Enable Signals and Start-up Time ....................................... 83 Interface to External Memory ............................................................ 84 Using the External Memory Interface ................................................................. 88 I/O Ports............................................................................................... 89 Port A.........
ATmega161(L) 40P6 ................................................................................................................. 151 Errata ................................................................................................. 152 ATmega161 Rev. E .......................................................................................... 152 Data Sheet Change Log for ATmega161 ........................................ 154 Changes from Rev. 1228B-09/01 to Rev. 1228C-08/02 ......................
iv ATmega161(L) 1228C–AVR–08/02
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