Manual
Table Of Contents
- Ordering Information
- Features
- Description
- Architectural Overview
- General Purpose Register File
- ALU - Arithmetic Logic Unit
- ISP Flash Program Memory
- SRAM Data Memory
- Program and Data Addressing Modes
- Register Direct, Single Register Rd
- Register Direct, Two Registers Rd and Rr
- I/O Direct
- Data Direct
- Data Indirect with Displacement
- Data Indirect
- Data Indirect With Pre-Decrement
- Data Indirect With Post-Increment
- Constant Addressing Using the LPM and ELPM Instructions
- Direct Program Address, JMP and CALL
- Indirect Program Addressing, IJMP and ICALL
- Relative Program Addressing, RJMP and RCALL
- EEPROM Data Memory
- Memory Access Times and Instruction Execution Timing
- I/O Memory
- Reset and Interrupt Handling
- Reset Sources
- Power-On Reset
- External Reset
- Watchdog Reset
- MCU Status Register - MCUSR
- Interrupt Handling
- External Interrupt Mask Register - EIMSK
- External Interrupt Flag Register - EIFR
- External Interrupt Control Register - EICR
- Timer/Counter Interrupt Mask Register - TIMSK
- Timer/Counter Interrupt Flag Register - TIFR
- Interrupt Response Time
- Sleep Modes
- Timer/Counters
- Timer/Counter Prescalers
- 8-bit Timer/Counters T/C0 and T/C2
- Timer/Counter0 Control Register - TCCR0
- Timer/Counter2 Control Register - TCCR2
- Timer/Counter0 - TCNT0
- Timer/Counter2 - TCNT2
- Timer/Counter0 Output Compare Register - OCR0
- Timer/Counter2 Output Compare Register - OCR2
- Timer/Counter 0 and 2 in PWM mode
- Asynchronous Status Register - ASSR
- Asynchronous Operation of Timer/Counter0
- 16-bit Timer/Counter1
- Timer/Counter1 Control Register A - TCCR1A
- Timer/Counter1 Control Register B - TCCR1B
- Timer/Counter1 - TCNT1H and TCNT1L
- Timer/Counter1 Output Compare Register - OCR1AH and OCR1AL
- Timer/Counter1 Output Compare Register - OCR1BH and OCR1BL
- Timer/Counter1 Input Capture Register - ICR1H and ICR1L
- Timer/Counter1 in PWM mode
- Watchdog Timer
- EEPROM Read/Write Access
- Serial Peripheral Interface - SPI
- UART
- Analog Comparator
- Analog to Digital Converter
- Interface to external SRAM
- I/O-Ports
- Memory Programming
- Electrical Characteristics
- Typical characteristics
- Register Summary
- Instruction Set Summary (Continued)
ATmega603/103
99
Reading The Flash
The algorithm for reading the Flash memory is as follows (refer to Programming the Flash for details on Command and
Address loading):
1. A: Load Command ‘0000 0010’.
2. H: Load Address High Byte ($00-$7F/$FF)
3. B: Load Address Low Byte ($00 - $FF)
4. Set OE
to ‘0’, and BS1 to ‘0’. The Flash word low byte can now be read at DATA
5. Set BS to ‘1’. The Flash word high byte can now be read at DATA
6. Set OE
to ‘1’.
Reading The EEPROM
The algorithm for reading the EEPROM memory is as follows (refer to Programming the Flash for details on Command and
Address loading):
1. A: Load Command ‘0000 0011’.
2. H: Load Address High Byte ($00-$07/$0F)
3. B: Load Address ($00 - $FF)
4. Set OE
to ‘0’, and BS1 to ‘0’. The EEPROM Data byte can now be read at DATA
5. Set OE
to ‘1’.
Programming The Fuse Bits
The algorithm for programming the Fuse bits is as follows (refer to Programming the Flash for details on Command and
Data loading):
1. A: Load Command ‘0100 0000’.
2. C: Load Data Low Byte. Bit n = ‘0’ programs and bit n = ‘1’ erases the Fuse bit.
Bit 5 = SPIEN Fuse bit
Bit 3 = EESAVE Fuse bit
Bit 2 = always ‘1’
Bit 1 = SUT1 Fuse bit
Bit 0 = SUT0 Fuse bit
Bit 7, 6,4,2 = ‘1’. These bits are reserved and should be left unprogrammed (‘1’).
3. Give WR
a t
WLWH_PFB
wide negative pulse to execute the programming, t
WLWH_PFB
is found in Table 42. Programming
the Fuse bits does not generate any activity on the RDY/BSY
pin.
Programming the Lock Bits
The algorithm for programming the Lock bits is as follows (refer to Programming the Flash for details on Command and
Data loading):
1. A: Load Command ‘0010 0000’.
2. D: Load Data Low Byte. Bit n = ‘0’ programs the Lock bit.
Bit 2 = Lock Bit2
Bit 1 = Lock Bit1
Bit 7-3,0 = ‘1’. These bits are reserved and should be left unprogrammed (‘1’).
3. L: Write Data Low Byte.
The Lock bits can only be cleared by executing Chip Erase.