Manual
Table Of Contents
- Ordering Information
- Features
- Description
- Architectural Overview
- General Purpose Register File
- ALU - Arithmetic Logic Unit
- ISP Flash Program Memory
- SRAM Data Memory
- Program and Data Addressing Modes
- Register Direct, Single Register Rd
- Register Direct, Two Registers Rd and Rr
- I/O Direct
- Data Direct
- Data Indirect with Displacement
- Data Indirect
- Data Indirect With Pre-Decrement
- Data Indirect With Post-Increment
- Constant Addressing Using the LPM and ELPM Instructions
- Direct Program Address, JMP and CALL
- Indirect Program Addressing, IJMP and ICALL
- Relative Program Addressing, RJMP and RCALL
- EEPROM Data Memory
- Memory Access Times and Instruction Execution Timing
- I/O Memory
- Reset and Interrupt Handling
- Reset Sources
- Power-On Reset
- External Reset
- Watchdog Reset
- MCU Status Register - MCUSR
- Interrupt Handling
- External Interrupt Mask Register - EIMSK
- External Interrupt Flag Register - EIFR
- External Interrupt Control Register - EICR
- Timer/Counter Interrupt Mask Register - TIMSK
- Timer/Counter Interrupt Flag Register - TIFR
- Interrupt Response Time
- Sleep Modes
- Timer/Counters
- Timer/Counter Prescalers
- 8-bit Timer/Counters T/C0 and T/C2
- Timer/Counter0 Control Register - TCCR0
- Timer/Counter2 Control Register - TCCR2
- Timer/Counter0 - TCNT0
- Timer/Counter2 - TCNT2
- Timer/Counter0 Output Compare Register - OCR0
- Timer/Counter2 Output Compare Register - OCR2
- Timer/Counter 0 and 2 in PWM mode
- Asynchronous Status Register - ASSR
- Asynchronous Operation of Timer/Counter0
- 16-bit Timer/Counter1
- Timer/Counter1 Control Register A - TCCR1A
- Timer/Counter1 Control Register B - TCCR1B
- Timer/Counter1 - TCNT1H and TCNT1L
- Timer/Counter1 Output Compare Register - OCR1AH and OCR1AL
- Timer/Counter1 Output Compare Register - OCR1BH and OCR1BL
- Timer/Counter1 Input Capture Register - ICR1H and ICR1L
- Timer/Counter1 in PWM mode
- Watchdog Timer
- EEPROM Read/Write Access
- Serial Peripheral Interface - SPI
- UART
- Analog Comparator
- Analog to Digital Converter
- Interface to external SRAM
- I/O-Ports
- Memory Programming
- Electrical Characteristics
- Typical characteristics
- Register Summary
- Instruction Set Summary (Continued)

ATmega603/103
96
Programming The Flash
The Flash is organized as 256/512 pages of 256 bytes each. When programming the Flash, the program data is latched
into a page buffer. This allows one page of program data to be programmed simultaneously. The following procedure
describes how to program the entire Flash memory:
A: Load Command “Write Flash”
1. Set XA1, XA0 to ‘10’. This enables command loading.
2. Set BS1 to ‘0’
3. Set DATA to ‘0001 0000’. This is the command for Write Flash.
4. Give XTAL1 a positive pulse. This loads the command.
B: Load Address Low Byte
1. Set XA1, XA0 to ‘00’. This enables address loading.
2. Set BS1 to ‘0’. This selects low address.
3. Set DATA = Address low byte ($00 - $FF)
4. Give XTAL1 a positive pulse. This loads the address low byte.
C: Load Data Low Byte
1. Set BS1 to ‘0’. This selects low data.
2. Set XA1, XA0 to ‘01’. This enables data loading.
3. Set DATA = Data low byte ($00 - $FF)
4. Give XTAL1 a positive pulse. This loads the data byte.
D: Latch Data Low byte
Give PAGEL a positive pulse, This latches the data low byte.
(See Figure 73 for signal waveforms.)
E: Load Data High Byte
1. Set BS1 to ‘1’. This selects high data.
2. Set XA1, XA0 to ‘01’. This enables data loading.
3. Set DATA = Data high byte ($00 - $FF)
4. Give XTAL1 a positive pulse. This loads the data high byte.
F: Latch Data High Byte
Give PAGEL a positive pulse. This latches the data high byte.
G: Repeat B through F 128 times to fill the page buffer
H: Load Address High Byte
1. Set XA1, XA0 to ‘00’. This enables address loading.
2. Set BS1 to ‘1’. This selects high address.
3. Set DATA = Address high byte ($00-$7F/$FF).
4. Give XTAL1 a positive pulse. This loads the address high byte.
I: Program Page
1. Give WR
a negative pulse. This starts programming of the entire page of data. RDY/BSY goes low.
2. Wait until RDY/BSY
goes high.
(See Figure 74 for signal waveforms.)
J: End Page Programming
1. Set XA1, XA0 to ‘10’. This enables command loading.
2. Set DATA = ‘0000 0000’. This is the command for No Operation.
3. Give XTAL1 a positive pulse. This loads the command and the internal write signals are reset.