Manual
Table Of Contents
- Ordering Information
- Features
- Description
- Architectural Overview
- General Purpose Register File
- ALU - Arithmetic Logic Unit
- ISP Flash Program Memory
- SRAM Data Memory
- Program and Data Addressing Modes
- Register Direct, Single Register Rd
- Register Direct, Two Registers Rd and Rr
- I/O Direct
- Data Direct
- Data Indirect with Displacement
- Data Indirect
- Data Indirect With Pre-Decrement
- Data Indirect With Post-Increment
- Constant Addressing Using the LPM and ELPM Instructions
- Direct Program Address, JMP and CALL
- Indirect Program Addressing, IJMP and ICALL
- Relative Program Addressing, RJMP and RCALL
- EEPROM Data Memory
- Memory Access Times and Instruction Execution Timing
- I/O Memory
- Reset and Interrupt Handling
- Reset Sources
- Power-On Reset
- External Reset
- Watchdog Reset
- MCU Status Register - MCUSR
- Interrupt Handling
- External Interrupt Mask Register - EIMSK
- External Interrupt Flag Register - EIFR
- External Interrupt Control Register - EICR
- Timer/Counter Interrupt Mask Register - TIMSK
- Timer/Counter Interrupt Flag Register - TIFR
- Interrupt Response Time
- Sleep Modes
- Timer/Counters
- Timer/Counter Prescalers
- 8-bit Timer/Counters T/C0 and T/C2
- Timer/Counter0 Control Register - TCCR0
- Timer/Counter2 Control Register - TCCR2
- Timer/Counter0 - TCNT0
- Timer/Counter2 - TCNT2
- Timer/Counter0 Output Compare Register - OCR0
- Timer/Counter2 Output Compare Register - OCR2
- Timer/Counter 0 and 2 in PWM mode
- Asynchronous Status Register - ASSR
- Asynchronous Operation of Timer/Counter0
- 16-bit Timer/Counter1
- Timer/Counter1 Control Register A - TCCR1A
- Timer/Counter1 Control Register B - TCCR1B
- Timer/Counter1 - TCNT1H and TCNT1L
- Timer/Counter1 Output Compare Register - OCR1AH and OCR1AL
- Timer/Counter1 Output Compare Register - OCR1BH and OCR1BL
- Timer/Counter1 Input Capture Register - ICR1H and ICR1L
- Timer/Counter1 in PWM mode
- Watchdog Timer
- EEPROM Read/Write Access
- Serial Peripheral Interface - SPI
- UART
- Analog Comparator
- Analog to Digital Converter
- Interface to external SRAM
- I/O-Ports
- Memory Programming
- Electrical Characteristics
- Typical characteristics
- Register Summary
- Instruction Set Summary (Continued)
ATmega603/103
95
Enter Programming Mode
The following algorithm puts the device in parallel programming mode:
1. Apply supply voltage according to Table 37, between V
CC
and GND.
2. Set RESET
and BS1 pins to ‘0’ and wait at least 100 ns.
3. Apply 11.5 - 12.5V to RESET
. Any activity on BS1 within 100 ns after +12V has been applied to RESET, will cause
the device to fail entering programming mode.
Chip Erase
The Chip Erase will erase the Flash and EEPROM memories, and Lock bits. The Lock bits are not reset until the program
memory has been completely erased. The Fuse bits are not changed. A chip erase must be performed before the Flash or
EEPROM is reprogrammed.
Load Command “Chip Erase”
1. Set XA1, XA0 to ‘10’. This enables command loading.
2. Set BS1 to ‘0’.
3. Set DATA to ‘1000 0000’. This is the command for Chip erase.
4. Give XTAL1 a positive pulse. This loads the command.
5. Give WR
a t
WLWH_CE
wide negative pulse to execute Chip Erase. See Table 41 for t
WLWH_CE
value. Chip Erase does
not generate any activity on the RDY/BSY
pin.
Table 40. Command Byte Bit Coding
Command Byte Command Executed
1000 0000 Chip Erase
0100 0000 Write Fuse Bits
0010 0000 Write Lock Bits
0001 0000 Write Flash
0001 0001 Write EEPROM
0000 1000 Read Signature Bytes
0000 0100 Read Lock and Fuse Bits
0000 0010 Read Flash
0000 0011 Read EEPROM
Table 41. Minimum WR pulse width for chip erase
Symbol 3.2V 3.6V 4.0V 5.0V
t
WLWH_CE
56 ms 43 ms 35 ms 22 ms