Manual
Table Of Contents
- Ordering Information
- Features
- Description
- Architectural Overview
- General Purpose Register File
- ALU - Arithmetic Logic Unit
- ISP Flash Program Memory
- SRAM Data Memory
- Program and Data Addressing Modes
- Register Direct, Single Register Rd
- Register Direct, Two Registers Rd and Rr
- I/O Direct
- Data Direct
- Data Indirect with Displacement
- Data Indirect
- Data Indirect With Pre-Decrement
- Data Indirect With Post-Increment
- Constant Addressing Using the LPM and ELPM Instructions
- Direct Program Address, JMP and CALL
- Indirect Program Addressing, IJMP and ICALL
- Relative Program Addressing, RJMP and RCALL
- EEPROM Data Memory
- Memory Access Times and Instruction Execution Timing
- I/O Memory
- Reset and Interrupt Handling
- Reset Sources
- Power-On Reset
- External Reset
- Watchdog Reset
- MCU Status Register - MCUSR
- Interrupt Handling
- External Interrupt Mask Register - EIMSK
- External Interrupt Flag Register - EIFR
- External Interrupt Control Register - EICR
- Timer/Counter Interrupt Mask Register - TIMSK
- Timer/Counter Interrupt Flag Register - TIFR
- Interrupt Response Time
- Sleep Modes
- Timer/Counters
- Timer/Counter Prescalers
- 8-bit Timer/Counters T/C0 and T/C2
- Timer/Counter0 Control Register - TCCR0
- Timer/Counter2 Control Register - TCCR2
- Timer/Counter0 - TCNT0
- Timer/Counter2 - TCNT2
- Timer/Counter0 Output Compare Register - OCR0
- Timer/Counter2 Output Compare Register - OCR2
- Timer/Counter 0 and 2 in PWM mode
- Asynchronous Status Register - ASSR
- Asynchronous Operation of Timer/Counter0
- 16-bit Timer/Counter1
- Timer/Counter1 Control Register A - TCCR1A
- Timer/Counter1 Control Register B - TCCR1B
- Timer/Counter1 - TCNT1H and TCNT1L
- Timer/Counter1 Output Compare Register - OCR1AH and OCR1AL
- Timer/Counter1 Output Compare Register - OCR1BH and OCR1BL
- Timer/Counter1 Input Capture Register - ICR1H and ICR1L
- Timer/Counter1 in PWM mode
- Watchdog Timer
- EEPROM Read/Write Access
- Serial Peripheral Interface - SPI
- UART
- Analog Comparator
- Analog to Digital Converter
- Interface to external SRAM
- I/O-Ports
- Memory Programming
- Electrical Characteristics
- Typical characteristics
- Register Summary
- Instruction Set Summary (Continued)
ATmega603/103
76
Figure 53. Port A Schematic Diagrams (Pins PA0 - PA7)
Port B
Port B is an 8-bit bi-directional I/O port with internal pull-ups.
Three I/O memory address locations are allocated for Port B, one each for the Data Register - PORTB, $18($38), Data
Direction Register - DDRB, $17($37) and the Port B Input Pins - PINB, $16($36). The Port B Input Pins address is read
only, while the Data Register and the Data Direction Register are read/write.
All port pins have individually selectable pull-up resistors. The Port B output buffers can sink 20mA and thus drive LED dis-
plays directly. When pins PB0 to PB7 are used as inputs and are externally pulled low, they will source current if the
internal pull-up resistors are activated.
DATA BUS
D
D
Q
Q
RESET
RESET
C
C
WD
WP
RD
RP
MOS
PULL-
UP
PAn
R
R
WP:
WD:
RL:
RP:
RD:
SRE:
A:
D:
W:
R:
n:
WRITE PORTA
WRITE DDRA
READ PORTA LATCH
READ PORTA PIN
READ DDRA
EXT. SRAM ENABLE
ADDRESS
DATA
WRITE
READ
0-7
DDAn
PORTAn
SRE
SRE
R
R
Dn
Dn
W
W
An
An
RL