Manual
Table Of Contents
- Ordering Information
- Features
- Description
- Architectural Overview
- General Purpose Register File
- ALU - Arithmetic Logic Unit
- ISP Flash Program Memory
- SRAM Data Memory
- Program and Data Addressing Modes
- Register Direct, Single Register Rd
- Register Direct, Two Registers Rd and Rr
- I/O Direct
- Data Direct
- Data Indirect with Displacement
- Data Indirect
- Data Indirect With Pre-Decrement
- Data Indirect With Post-Increment
- Constant Addressing Using the LPM and ELPM Instructions
- Direct Program Address, JMP and CALL
- Indirect Program Addressing, IJMP and ICALL
- Relative Program Addressing, RJMP and RCALL
- EEPROM Data Memory
- Memory Access Times and Instruction Execution Timing
- I/O Memory
- Reset and Interrupt Handling
- Reset Sources
- Power-On Reset
- External Reset
- Watchdog Reset
- MCU Status Register - MCUSR
- Interrupt Handling
- External Interrupt Mask Register - EIMSK
- External Interrupt Flag Register - EIFR
- External Interrupt Control Register - EICR
- Timer/Counter Interrupt Mask Register - TIMSK
- Timer/Counter Interrupt Flag Register - TIFR
- Interrupt Response Time
- Sleep Modes
- Timer/Counters
- Timer/Counter Prescalers
- 8-bit Timer/Counters T/C0 and T/C2
- Timer/Counter0 Control Register - TCCR0
- Timer/Counter2 Control Register - TCCR2
- Timer/Counter0 - TCNT0
- Timer/Counter2 - TCNT2
- Timer/Counter0 Output Compare Register - OCR0
- Timer/Counter2 Output Compare Register - OCR2
- Timer/Counter 0 and 2 in PWM mode
- Asynchronous Status Register - ASSR
- Asynchronous Operation of Timer/Counter0
- 16-bit Timer/Counter1
- Timer/Counter1 Control Register A - TCCR1A
- Timer/Counter1 Control Register B - TCCR1B
- Timer/Counter1 - TCNT1H and TCNT1L
- Timer/Counter1 Output Compare Register - OCR1AH and OCR1AL
- Timer/Counter1 Output Compare Register - OCR1BH and OCR1BL
- Timer/Counter1 Input Capture Register - ICR1H and ICR1L
- Timer/Counter1 in PWM mode
- Watchdog Timer
- EEPROM Read/Write Access
- Serial Peripheral Interface - SPI
- UART
- Analog Comparator
- Analog to Digital Converter
- Interface to external SRAM
- I/O-Ports
- Memory Programming
- Electrical Characteristics
- Typical characteristics
- Register Summary
- Instruction Set Summary (Continued)
ATmega603/103
70
ADC Control and Status Register - ADCSR
•
Bit 7 - ADEN: ADC Enable
Writing a logical ‘1’ to this bit enables the ADC. By clearing this bit to zero, the ADC is turned off. Turning the ADC off while
a conversion is in progress, will terminate this conversion.
•
Bit 6 - ADSC: ADC Start Conversion
A logical ‘1’ must be written to this bit to start each conversion. The first time ADSC has been written after the ADC has
been enabled, or if ADSC is written at the same time as the ADC is enabled, a dummy conversion will precede the initiated
conversion. This dummy conversion performs initialization of the ADC.
ADSC remains high during the conversion. ADSC goes low after the conversion is complete, but before the result is written
to the ADC Data Registers. This allows a new conversion to be initiated before the current conversion is complete. The new
conversion will then start immediately after the current conversion completes. When a dummy conversion precedes a real
conversion, ADSC will stay high until the real conversion completes.
Writing a zero to this bit has no effect.
•
Bit 5 - Res: Reserved Bit
This bit is reserved in the ATmega603/103. Warning: When writing ADCSR, a logical “0” must be written to this bit.
•
Bit 4 -ADIF: ADC Interrupt Flag
This bit is set (one) when an ADC conversion is complete and the the result is written to the ADC Data Registers are
updated. The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set (one). ADIF is
cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a
logical one to the flag. Beware that if doing a read-modify-write on ADCSR, a pending interrupt can be disabled. This also
applies if the SBI and CBI instructions are used.
•
Bit 3 - ADIE: ADC Interrupt Enable
When this bit is set (one) and the I-bit in SREG is set (one), the ADC Conversion Complete Interrupt is activated.
•
Bits 2..0 - ADPS2..ADPS0: ADC Prescaler Select Bits
These bits determine the division factor between the XTAL frequency and the input clock to the ADC.
Bit 76543210
$06 ($26) ADEN ADSC - ADIF ADIE ADPS2 ADPS1 ADPS0 ADCSR
Read/Write R/W R/W R R/W R/W R/W R/W R/W
Initial value00000000
Table 28. ADC Prescaler Selections
ADPS2 ADPS1 ADPS0 Division Factor
000 Invalid
001 2
010 4
011 8
100 16
101 32
110 64
111 128