Manual
Table Of Contents
- Ordering Information
- Features
- Description
- Architectural Overview
- General Purpose Register File
- ALU - Arithmetic Logic Unit
- ISP Flash Program Memory
- SRAM Data Memory
- Program and Data Addressing Modes
- Register Direct, Single Register Rd
- Register Direct, Two Registers Rd and Rr
- I/O Direct
- Data Direct
- Data Indirect with Displacement
- Data Indirect
- Data Indirect With Pre-Decrement
- Data Indirect With Post-Increment
- Constant Addressing Using the LPM and ELPM Instructions
- Direct Program Address, JMP and CALL
- Indirect Program Addressing, IJMP and ICALL
- Relative Program Addressing, RJMP and RCALL
- EEPROM Data Memory
- Memory Access Times and Instruction Execution Timing
- I/O Memory
- Reset and Interrupt Handling
- Reset Sources
- Power-On Reset
- External Reset
- Watchdog Reset
- MCU Status Register - MCUSR
- Interrupt Handling
- External Interrupt Mask Register - EIMSK
- External Interrupt Flag Register - EIFR
- External Interrupt Control Register - EICR
- Timer/Counter Interrupt Mask Register - TIMSK
- Timer/Counter Interrupt Flag Register - TIFR
- Interrupt Response Time
- Sleep Modes
- Timer/Counters
- Timer/Counter Prescalers
- 8-bit Timer/Counters T/C0 and T/C2
- Timer/Counter0 Control Register - TCCR0
- Timer/Counter2 Control Register - TCCR2
- Timer/Counter0 - TCNT0
- Timer/Counter2 - TCNT2
- Timer/Counter0 Output Compare Register - OCR0
- Timer/Counter2 Output Compare Register - OCR2
- Timer/Counter 0 and 2 in PWM mode
- Asynchronous Status Register - ASSR
- Asynchronous Operation of Timer/Counter0
- 16-bit Timer/Counter1
- Timer/Counter1 Control Register A - TCCR1A
- Timer/Counter1 Control Register B - TCCR1B
- Timer/Counter1 - TCNT1H and TCNT1L
- Timer/Counter1 Output Compare Register - OCR1AH and OCR1AL
- Timer/Counter1 Output Compare Register - OCR1BH and OCR1BL
- Timer/Counter1 Input Capture Register - ICR1H and ICR1L
- Timer/Counter1 in PWM mode
- Watchdog Timer
- EEPROM Read/Write Access
- Serial Peripheral Interface - SPI
- UART
- Analog Comparator
- Analog to Digital Converter
- Interface to external SRAM
- I/O-Ports
- Memory Programming
- Electrical Characteristics
- Typical characteristics
- Register Summary
- Instruction Set Summary (Continued)
ATmega603/103
67
An external reference voltage must be applied to the AREF pin. This voltage must be in the range AGND - AV
CC
.
Figure 45. Analog to Digital Converter Block Schematic
Operation
The ADC operates in Single Conversion mode, and each conversion will have to be initiated by the user.
The ADC is enabled by writing a logical one to the ADC Enable bit, ADEN in ADCSR. The first conversion that is started
after enabling the ADC, will be preceded by a dummy conversion to initialize the ADC. To the user, the only difference will
be that this conversion takes 13 more ADC clock pulses than a normal conversion. (See Figure 48.)
A conversion is started by writing a logical one to the ADC Start Conversion bit, ADSC. This bit will stay high as long as the
conversion is in progress and be set to zero by hardware when the conversion is completed. If a different data channel is
selected while a conversion is in progress, the ADC will finish the current conversion before performing the channel
change.
As the ADC generates a 10-bit result, two data registers, ADCH and ADCL, must be read to get the result when the conver-
sion is complete. Special data protection logic is used to ensure that the contents of the data registers belong to the same
result when they are read. This mechanism works as follows:
When reading data, ADCL must be read first. Once ADCL is read, ADC access to data registers is blocked. This means
that if ADCL has been read, and a conversion completes before ADCH is read, none of the registers are updated and the
result from the conversion is lost. When ADCH is read, ADC access to the ADCH and ADCL registers is re-enabled.
The ADC has its own interrupt, ADIF, which can be triggered when a conversion completes. When ADC access to the data
registers is prohibited between reading of ADCL and ADCH, the interrupt will trigger even if the result is lost.
ADC CONVERSION
COMPLETE IRQ
8-BIT DATA BUS
90
ADC MULTIPLEXER
SELECT (ADMUX)
ADC CTRL & STATUS
REGISTER (ADCSR)
ADC DATA REGISTER
(ADCH/ADCL)
MUX2
ADIE
ADIE
ADSC
ADEN
ADIF
ADIF
MUX1
MUX0
ADPS0
ADPS1
ADPS2
8-
CHANNEL
MUX
CONVERSION LOGIC10-BIT DAC
+
-
SAMPLE & HOLD
COMPARATOR
Analog
Inputs
External
Reference
Voltage