Manual

ATmega603/103
65
UART Baud Rate Register - UBRR
The UBRR is an 8-bit read/write register which specifies the UART Baud Rate according to the description on the previous
page.
Analog Comparator
The analog comparator compares the input values on the positive input PE2 (AC+) and negative input PE3 (AC-). When
the voltage on the positive input PE2 (AC+) is higher than the voltage on the negative input PE3 (AC-), the Analog Compar-
ator Output, ACO is set (one). The output of the comparator can be set to trigger the Timer/Counter1 Input Capture
function. In addition, the comparator can trigger a separate interrupt, exclusive to the Analog Comparator. The user can
select Interrupt triggering on comparator output rise, fall, or toggle. A block diagram of the comparator and its surrounding
logic is shown in Figure 44.
Figure 44. Analog Comparator Block Diagram
Analog Comparator Control and Status Register - ACSR
•
Bit 7 - ACD: Analog Comparator Disable
When this bit is set(one), the power to the analog comparator is switched off. This bit can be set at any time to turn off the
analog comparator. This will reduce power consumption in active and idle mode. When changing the ACD bit, the Analog
Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is
changed.
•
Bit 6 - Res: Reserved bit
This bit is a reserved bit in the ATmega603/103 and will always read as zero.
•
Bit 5 - ACO: Analog Comparator Output
ACO is directly connected to the comparator output.
Bit 76543210
$09 ($29) MSB LSB UBRR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value00000000
Bit 76543210
$08 ($28) ACD - ACO ACI ACIE ACIC ACIS1 ACIS0 ACSR
Read/Write R/W R R R/W R/W R/W R/W R/W
Initial value00000000
PE2
(AC+)
PE3
(AC-)
+
-
ACO
ACI
INTERRUPT
SELECT
ACIS1 ACIS0
ACIE
ACIC
ANALOG
COMPARATOR
IRQ
TO T/C1 CAPTURE
TRIGGER MUX
VCC
ACD