Manual
Table Of Contents
- Ordering Information
- Features
- Description
- Architectural Overview
- General Purpose Register File
- ALU - Arithmetic Logic Unit
- ISP Flash Program Memory
- SRAM Data Memory
- Program and Data Addressing Modes
- Register Direct, Single Register Rd
- Register Direct, Two Registers Rd and Rr
- I/O Direct
- Data Direct
- Data Indirect with Displacement
- Data Indirect
- Data Indirect With Pre-Decrement
- Data Indirect With Post-Increment
- Constant Addressing Using the LPM and ELPM Instructions
- Direct Program Address, JMP and CALL
- Indirect Program Addressing, IJMP and ICALL
- Relative Program Addressing, RJMP and RCALL
- EEPROM Data Memory
- Memory Access Times and Instruction Execution Timing
- I/O Memory
- Reset and Interrupt Handling
- Reset Sources
- Power-On Reset
- External Reset
- Watchdog Reset
- MCU Status Register - MCUSR
- Interrupt Handling
- External Interrupt Mask Register - EIMSK
- External Interrupt Flag Register - EIFR
- External Interrupt Control Register - EICR
- Timer/Counter Interrupt Mask Register - TIMSK
- Timer/Counter Interrupt Flag Register - TIFR
- Interrupt Response Time
- Sleep Modes
- Timer/Counters
- Timer/Counter Prescalers
- 8-bit Timer/Counters T/C0 and T/C2
- Timer/Counter0 Control Register - TCCR0
- Timer/Counter2 Control Register - TCCR2
- Timer/Counter0 - TCNT0
- Timer/Counter2 - TCNT2
- Timer/Counter0 Output Compare Register - OCR0
- Timer/Counter2 Output Compare Register - OCR2
- Timer/Counter 0 and 2 in PWM mode
- Asynchronous Status Register - ASSR
- Asynchronous Operation of Timer/Counter0
- 16-bit Timer/Counter1
- Timer/Counter1 Control Register A - TCCR1A
- Timer/Counter1 Control Register B - TCCR1B
- Timer/Counter1 - TCNT1H and TCNT1L
- Timer/Counter1 Output Compare Register - OCR1AH and OCR1AL
- Timer/Counter1 Output Compare Register - OCR1BH and OCR1BL
- Timer/Counter1 Input Capture Register - ICR1H and ICR1L
- Timer/Counter1 in PWM mode
- Watchdog Timer
- EEPROM Read/Write Access
- Serial Peripheral Interface - SPI
- UART
- Analog Comparator
- Analog to Digital Converter
- Interface to external SRAM
- I/O-Ports
- Memory Programming
- Electrical Characteristics
- Typical characteristics
- Register Summary
- Instruction Set Summary (Continued)
ATmega603/103
58
•
Bit 4 - MSTR: Master/Slave Select
This bit selects Master SPI mode when set (one), and Slave SPI mode when cleared (zero). If SS is configured as an input
and is driven low while MSTR is set, MSTR will be cleared, and SPIF in SPSR will become set. The user will then have to
set MSTR to re-enable SPI master mode.
•
Bit 3 - CPOL: Clock Polarity
When this bit is set (one), SCK is high when idle. When CPOL is cleared (zero), SCK is low when idle. Refer to Figure 39
and Figure 40 for additional information.
•
Bit 2 - CPHA: Clock Phase
Refer to Figure 39 or Figure 40 for the functionality of this bit.
•
Bits 1,0 - SPR1, SPR0: SPI Clock Rate Select 1 and 0
These two bits control the SCK rate of the device configured as a master. SPR1 and SPR0 have no effect on the slave. The
relationship between SCK and the CPU Clock frequency f
cl
is shown in the following table:
Note: Observe that CPU clock frequency can be lower than the XTAL frequency if the XTAL divider is enabled.
SPI Status Register - SPSR
•
Bit 7 - SPIF: SPI Interrupt Flag
When a serial transfer is complete, the SPIF bit is set (one) and an interrupt is generated if SPIE in SPCR is set (one) and
global interrupts are enabled. SPIF is cleared by hardware when executing the corresponding interrupt handling vector.
Alternatively, the SPIF bit is cleared by first reading the SPI status register with SPIF set (one), then accessing the SPI
Data Register (SPDR).
•
Bit 6 - WCOL: Write Collision flag
The WCOL bit is set if the SPI data register (SPDR) is written during a data transfer. The WCOL bit (and the SPIF bit) are
cleared (zero) by first reading the SPI Status Register with WCOL set (one), and then accessing the SPI Data Register.
•
Bit 5..0 - Res: Reserved bits
These bits are reserved bits in the ATmega603/103 and will always read as zero.
SPI Data Register - SPDR
The SPI Data Register is a read/write register used for data transfer between the register file and the SPI Shift register.
Writing to the register initiates data transmission. Reading the register causes the Shift Register Receive buffer to be read.
Table 24. Relationship Between SCK and the Oscillator Frequency
SPR1 SPR0 SCK Frequency
00
f
cl
/ 4
01
f
cl
/ 16
10
f
cl
/ 64
11
f
cl
/ 128
Bit 76543210
$0E SPIF WCOL - - - - - - SPSR
Read/WriteRRRRRRRR
Initial value00000000
Bit 76543210
$0F ($2F) MSB LSB SPDR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value
XXXXXXXXUndefined