Manual
Table Of Contents
- Ordering Information
- Features
- Description
- Architectural Overview
- General Purpose Register File
- ALU - Arithmetic Logic Unit
- ISP Flash Program Memory
- SRAM Data Memory
- Program and Data Addressing Modes
- Register Direct, Single Register Rd
- Register Direct, Two Registers Rd and Rr
- I/O Direct
- Data Direct
- Data Indirect with Displacement
- Data Indirect
- Data Indirect With Pre-Decrement
- Data Indirect With Post-Increment
- Constant Addressing Using the LPM and ELPM Instructions
- Direct Program Address, JMP and CALL
- Indirect Program Addressing, IJMP and ICALL
- Relative Program Addressing, RJMP and RCALL
- EEPROM Data Memory
- Memory Access Times and Instruction Execution Timing
- I/O Memory
- Reset and Interrupt Handling
- Reset Sources
- Power-On Reset
- External Reset
- Watchdog Reset
- MCU Status Register - MCUSR
- Interrupt Handling
- External Interrupt Mask Register - EIMSK
- External Interrupt Flag Register - EIFR
- External Interrupt Control Register - EICR
- Timer/Counter Interrupt Mask Register - TIMSK
- Timer/Counter Interrupt Flag Register - TIFR
- Interrupt Response Time
- Sleep Modes
- Timer/Counters
- Timer/Counter Prescalers
- 8-bit Timer/Counters T/C0 and T/C2
- Timer/Counter0 Control Register - TCCR0
- Timer/Counter2 Control Register - TCCR2
- Timer/Counter0 - TCNT0
- Timer/Counter2 - TCNT2
- Timer/Counter0 Output Compare Register - OCR0
- Timer/Counter2 Output Compare Register - OCR2
- Timer/Counter 0 and 2 in PWM mode
- Asynchronous Status Register - ASSR
- Asynchronous Operation of Timer/Counter0
- 16-bit Timer/Counter1
- Timer/Counter1 Control Register A - TCCR1A
- Timer/Counter1 Control Register B - TCCR1B
- Timer/Counter1 - TCNT1H and TCNT1L
- Timer/Counter1 Output Compare Register - OCR1AH and OCR1AL
- Timer/Counter1 Output Compare Register - OCR1BH and OCR1BL
- Timer/Counter1 Input Capture Register - ICR1H and ICR1L
- Timer/Counter1 in PWM mode
- Watchdog Timer
- EEPROM Read/Write Access
- Serial Peripheral Interface - SPI
- UART
- Analog Comparator
- Analog to Digital Converter
- Interface to external SRAM
- I/O-Ports
- Memory Programming
- Electrical Characteristics
- Typical characteristics
- Register Summary
- Instruction Set Summary (Continued)

ATmega603/103
5
Port E (PE7..PE0)
Port E is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port E output buffers can sink 20 mA. As inputs,
Port E pins that are externally pulled low will source current if the pull-up resistors are activated.
Port E also serves the functions of various special features.
The port E pins are tri-stated when a reset condition becomes active, even if the clock is not running
Port F (PF7..PF0)
Port F is an 8-bit Input port. Port F also serves as the analog inputs for the ADC.
RESET
Reset input. An external reset is generated by a low level on the RESET pin. Reset pulses longer than 50 ns will generate
a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.
XTAL1
Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier
TOSC1
Input to the inverting Timer/Counter oscillator amplifier
TOSC2
Output from the inverting Timer/Counter oscillator amplifier
WR
External SRAM Write Strobe.
RD
External SRAM Read Strobe.
ALE
ALE is the Address Latch Enable used when the External Memory is enabled. The ALE strobe is used to latch the low-
order address (8 bits) into an address latch during the first access cycle, and the AD0-7 pins are used for data during the
second access cycle.
AVCC
This is the supply voltage to the A/D Converter. It should be externally connected to V
CC
via a low-pass filter. See page 66
for details on operation of the ADC.
AREF
This is the analog reference input for the ADC converter. For ADC operations, a voltage in the range AGND to AVCC must
be applied to this pin.
AGND
If the board has a separate analog ground plane, this pin should be connected to this ground plane. Otherwise, connect to
GND.
PEN
This is a programming enable pin for the low-voltage serial programming mode. By holding this pin low during a power-on
reset, the device will enter the serial programming mode. PEN
has no function during normal operation.