Manual

ATmega603/103
24
Reset and Interrupt Handling
The ATmega603/103 provides 23 different interrupt sources. These interrupts and the separate reset vector each have a
separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be set
(one) together with the I-bit in the status register in order to enable the interrupt.
The lowest addresses in the program memory space are automatically defined as the Reset and Interrupt vectors. The
complete list of vectors is shown in Table 5. The list also determines the priority levels of the different interrupts. The lower
the address the higher is the priority level. RESET has the highest priority, and next is INT0 - the External Interrupt Request
0 etc.
Table 5. Reset and Interrupt Vectors
Vector No. Program Address Source Interrupt Definition
1 $0000 RESET Hardware Pin, Power-on Reset and Watchdog Reset
2 $0002 INT0 External Interrupt Request 0
3 $0004 INT1 External Interrupt Request 1
4 $0006 INT2 External Interrupt Request 2
5 $0008 INT3 External Interrupt Request 3
6 $000A INT4 External Interrupt Request 4
7 $000C INT5 External Interrupt Request 5
8 $000E INT6 External Interrupt Request 6
9 $0010 INT7 External Interrupt Request 7
10 $0012 TIMER2 COMP Timer/Counter2 Compare Match
11 $0014 TIMER2 OVF Timer/Counter2 Overflow
12 $0016 TIMER1 CAPT Timer/Counter1 Capture Event
13 $0018 TIMER1 COMPA Timer/Counter1 Compare Match A
14 $001A TIMER1 COMPB Timer/Counter1 Compare Match B
15 $001C TIMER1 OVF Timer/Counter1 Overflow
16 $001E TIMER0 COMP Timer/Counter0 Compare Match
17 $0020 TIMER0 OVF Timer/Counter0 Overflow
18 $0022 SPI, STC SPI Serial Transfer Complete
19 $0024 UART, RX UART, Rx Complete
20 $0026 UART, UDRE UART Data Register Empty
21 $0028 UART, TX UART, Tx Complete
22 $002A ADC ADC Conversion Complete
23 $002C EE READY EEPROM Ready
24 $002E ANALOG COMP Analog Comparator