Features • Utilizes the AVR® RISC Architecture • AVR - High-performance and Low-power RISC Architecture • • • • • • • • – 120/121 Powerful Instructions - Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers + Peripheral Control Registers – Up to 6 MIPS Throughput at 6 MHz Data and Nonvolatile Program Memory – 64K/128K Bytes of In-System Programmable Flash Endurance: 1,000 Write/Erase Cycles – 4K Bytes Internal SRAM – 2K/4K Bytes of In-System Programmable EEPROM Endurance: 100,0
Pin Configuration TQFP Description The ATmega603/103 is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega603/103 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. The AVR core is based on an enhanced RISC architecture that combines a rich instruction set with 32 general purpose working registers.
ATmega603/103 Block Diagram Figure 1. The ATmega603/103 Block Diagram VCC GND PORTF BUFFERS PORTA DRIVER/BUFFERS PORTC DRIVERS AVCC ANALOG MUX ADC DATA REGISTER PORTA DATA DIR. REG.
Comparison Between ATmega603 and ATmega103 The ATmega603 has 64K bytes of In-System Programmable Flash, 2K bytes of EEPROM, and 4K bytes of internal SRAM. The ATmega603 does not have the ELPM instruction. The ATmega103 has 128K bytes of In-System Programmable Flash, 4K bytes of EEPROM, and 4K bytes of internal SRAM. The ATmega103 has the ELPM instruction, necessary to reach the upper half of the Flash memory for constant table lookup. Table 1 summarizes the different memory sizes for the two devices.
ATmega603/103 Port E (PE7..PE0) Port E is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port E output buffers can sink 20 mA. As inputs , Port E pins that are externally pulled low will source current if the pull-up resistors are activated. Port E also serves the functions of various special features. The port E pins are tri-stated when a reset condition becomes active, even if the clock is not running Port F (PF7..PF0) Port F is an 8-bit Input port.
Clock Options Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an onchip oscillator, as shown in Figure 2. Either a quartz crystal or a ceramic resonator may be used. Figure 2. Oscillator Connections MAX 1 HC BUFFER HC C2 C1 XTAL2 XTAL1 GND Note: When using the MCU Oscillator as a clock for an external device, an HC buffer should be connected as indicated in the figure.
ATmega603/103 Architectural Overview Figure 4. The ATmega603/103 AVR RISC Architecture AVR ATmega603/103 Architecture Data Bus 8-bit 32K/64K x 16 Program Memory Program Counter Status and Test 32 x 8 General Purpose Registers Instruction Register Instruction Decoder IndirectAddressing DirectAddressing Control Lines Peripherals ALU 4K x 8 Data SRAM 2K/4K x 8 EEPROM The AVR uses a Harvard architecture concept - with separate memories and buses for program and data.
A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the status register. All the different interrupts have a separate interrupt vector in the interrupt vector table at the beginning of the program memory. The different interrupts have priority in accordance with their interrupt vector position. The lower the interrupt vector address, the higher the priority. The memory spaces in the AVR architecture are all linear and regular memory maps.
ATmega603/103 X-register, Y-register and Z-register The registers R26..R31 have some added functions to their general purpose usage. These registers are address pointers for indirect addressing of the SRAM. The three indirect address registers X, Y and Z are defined as: Figure 6.
Figure 7.
ATmega603/103 The 4096 first Data Memory locations address both the Register file, the I/O Memory and the internal data SRAM. The first 96 locations address the register file and I/O memory, and the next 4000 locations address the internal data SRAM. An optional external data SRAM can be used with the ATmega603/103. This SRAM will occupy an area in the remaining address locations in the 64K address space. This area starts at the address following the internal SRAM.
Register Direct, Two Registers Rd and Rr Figure 9. Direct Register Addressing, Two Registers REGISTER FILE 0 15 9 5 4 OP 0 r d d r 31 Operands are contained in register r (Rr) and d (Rd). The result is stored in register d (Rd). I/O Direct Figure 10. I/O Direct Addressing I/O MEMORY 0 5 15 OP n 0 P 63 Operand address is contained in 6 bits of the instruction word. n is the destination or source register address.
ATmega603/103 Data Direct Figure 11. Direct Data Addressing Data Space 20 19 31 OP $0000 16 Rr/Rd 16 LSBs 15 0 $FFFF A 16-bit Data Address is contained in the 16 LSBs of a two-word instruction. Rd/Rr specify the destination or source register. Data Indirect with Displacement Figure 12.
Data Indirect Figure 13. Data Indirect Addressing Data Space $0000 15 0 X, Y OR Z - REGISTER $FFFF Operand address is the contents of the X, Y or the Z-register. Data Indirect With Pre-Decrement Figure 14. Data Indirect Addressing with Pre-Decrement Data Space $0000 15 0 X, Y OR Z - REGISTER -1 $FFFF The X, Y or the Z-register is decremented before the operation. Operand address is the decremented contents of the X, Y or the Z-register.
ATmega603/103 Data Indirect With Post-Increment Figure 15. Data Indirect Addressing with Post-Increment Data Space $0000 15 0 X, Y OR Z - REGISTER 1 $FFFF The X, Y or the Z-register is incremented after the operation. Operand address is the content of the X, Y or the Z-register prior to incrementing. Constant Addressing Using the LPM and ELPM Instructions Figure 16.
Direct Program Address, JMP and CALL Figure 17. Direct Program Memory Addressing PROGRAM MEMORY $0000 31 21 20 16 OP 16 LSBs 15 0 $7FFF/$FFFF Program execution continues at the address immediate in the instruction words. Indirect Program Addressing, IJMP and ICALL Figure 18. Indirect Program Memory Addressing PROGRAM MEMORY $0000 15 0 Z - REGISTER $7FFF/$FFFF Program execution continues at address contained by the Z-register (i.e. the PC is loaded with the contents of the Z-register).
ATmega603/103 Relative Program Addressing, RJMP and RCALL Figure 19. Relative Program Memory Addressing PROGRAM MEMORY $0000 15 0 PC 15 0 12 11 OP k $7FFF/$FFFF Program execution continues at address PC + k + 1. The relative address k is -2048 to 2047. EEPROM Data Memory The EEPROM memory is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles.
Figure 21. Single Cycle ALU Operation T1 T2 T3 T4 System Clock Ø Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back The internal data SRAM access is performed in two System Clock cycles as described in Figure 22. Figure 22. On-Chip Data SRAM Access Cycles T1 T2 T3 T4 System Clock Ø Address Data WR Data RD See “Interface to external SRAM” on page 72 for a description of the access to the external SRAM. 18 ATmega603/103 Write Prev.
ATmega603/103 I/O Memory The I/O space definition of the ATmega603/103 is shown in the following table: Table 3.
Table 3.
ATmega603/103 The different I/O and peripherals control registers are explained in the following sections. Status Register - SREG The AVR status register - SREG - at I/O space location $3F ($5F) is defined as: Bit 7 6 5 4 3 2 1 0 $3F ($5F) I T H S V N Z C Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 SREG • Bit 7 - I: Global Interrupt Enable The global interrupt enable bit must be set (one) for the interrupts to be enabled.
The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The stack pointer must be set to point above $60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when an address is pushed onto the Stack with subroutine calls and interrupts.
ATmega603/103 • Bits 4,3 - SM1/SM0: Sleep Mode Select bits 1 and 0 This bit selects between the three available sleep modes as shown in the following table: Table 4. Sleep Mode Select SM1 SM0 Sleep Mode 0 0 Idle Mode 0 1 Reserved 1 0 Power Down 1 1 Power Save • Bits 2..0 - Res: Reserved bits These bits are reserved bits in the ATmega603/103 and always read zero.
Reset and Interrupt Handling The ATmega603/103 provides 23 different interrupt sources. These interrupts and the separate reset vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be set (one) together with the I-bit in the status register in order to enable the interrupt. The lowest addresses in the program memory space are automatically defined as the Reset and Interrupt vectors.
ATmega603/103 The most typical program setup for the Reset and Interrupt Vector Addresses are: Address Labels Code Comments $0000 jmp RESET ; Reset Handler $0002 jmp EXT_INT0 ; IRQ0 Handler $0004 jmp EXT_INT1 ; IRQ1 Handler $0006 jmp EXT_INT2 ; IRQ2 Handler $0008 jmp EXT_INT3 ; IRQ3 Handler $000A jmp EXT_INT4 ; IRQ4 Handler $000C jmp EXT_INT5 ; IRQ5 Handler $000E jmp EXT_INT6 ; IRQ6 Handler $0010 jmp EXT_INT7 ; IRQ7 Handler $0012 jmp TIM2_COMP ; Timer2 Compare Hand
Figure 23. Reset Logic Power-On Reset Circuit PEN D Q Reset Circuit Watchdog Timer E On-Chip RC-Oscillator 14-Stage Ripple Counter Q8 S Q R Q SUT0 SUT1 RESET POR COUNTER RESET 10-50K 100-500K VCC Q11 Q13 INTERNAL RESET Delay Unit XTAL1 Table 6. Reset Characteristics (VCC = 5V) Symbol VPOT(1) VRST Parameter Condition Min Typ Max Units Power-On Reset Threshold (rising) 1.0 1.4 1.8 V Power-On Reset Threshold (falling) 0.4 0.6 0.
ATmega603/103 Power-On Reset A Power-On Reset (POR) circuit ensures that the device is reset from power-on. As shown in Figure 23, an internal timer clocked from the Watchdog timer oscillator prevents the MCU from starting until after a certain period after V CC has reached the Power-On Threshold voltage - VPOT, regardless of the VCC rise time (see Figure 24). The Fuse bits SUT1 and SUT0 is used to select start-up time as indicated in Table 6. A “0” in the table indicates that the fuse is programmed.
Figure 25. MCU Start-Up, RESET Controlled Externally VCC VPOT VRST RESET tTOUT TIME-OUT INTERNAL RESET External Reset An external reset is generated by a low level on the RESET pin. Reset pulses longer than 50 ns will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold Voltage - VRST - on its positive edge, the delay timer starts the MCU after the Time-out period tTOUT has expired. Figure 26.
ATmega603/103 Figure 27. Watchdog Reset During Operation VCC RESET 1 XTAL Cycle WDT TIME-OUT tTOUT RESET TIME-OUT INTERNAL RESET MCU Status Register - MCUSR The MCU Status Register provides information on which reset source caused an MCU reset. Bit 7 6 5 4 3 2 1 0 $34 ($54) - - - - - - EXTRF PORF Read/Write R R R R R R R/W R/W Initial value 0 0 0 0 0 0 MCUSR See bit description • Bits 7..
Interrupt Handling The ATmega603/103 has two dedicated 8-bit Interrupt Mask control registers; EIMSK - External Interrupt Mask register and TIMSK - Timer/Counter Interrupt Mask register. In addition, other enable and mask bits can be found in the peripheral control registers. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all interrupts are disabled. The user software can set (one) the I-bit to enable nested interrupts.
ATmega603/103 External Interrupt Control Register - EICR Bit 7 6 5 4 3 2 1 0 $3A ($5A) ISC71 ISC70 ISC61 ISC60 ISC51 ISC50 ISC41 ISC40 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 EICR • Bits 7..0 - ISCX1, ISCX0: External Interrupt 7-4 Sense Control bits The External Interrupts 7 - 4 are activated by the external pins INT7 - INT4 if the SREG I-flag and the corresponding interrupt mask in the EIMSK is set.
• Bit 3 - OCIE1B: Timer/Counter1 Output CompareB Match Interrupt Enable When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareB Match interrupt is enabled. The corresponding interrupt (at vector $001A) is executed if a CompareB match in Timer/Counter1 occurs, i.e., when the OCF1B bit is set in the Timer/Counter Interrupt Flag Register - TIFR.
ATmega603/103 • Bit 2 - TOV1: Timer/Counter1 Overflow Flag The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV1 is cleared by writing a logic one to the flag. When the I-bit in SREG, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and TOV1 are set (one), the Timer/Counter1 Overflow Interrupt is executed. In PWM mode, this bit is set when Timer/Counter1 advances from $0000.
Power Down Mode When the SM1/SM0 bits are set to 10, the SLEEP instruction makes the MCU enter the Power Down Mode. In this mode, the external oscillator is stopped, while the external interrupts and the Watchdog (if enabled) continue operating. Only an external reset, a watchdog reset (if enabled), or an external level interrupt can wake up the MCU. Note that if a level triggered interrupt is used for wake-up from Power Down Mode, the changed level must be held for some time to wake up the MCU.
ATmega603/103 Timer/Counter Prescalers Figure 28. Prescaler for Timer/Counter 1 and Timer/Counter2 CK CK/1024 CK/8 CK/64 CK/256 10-BIT T/C PRESCALER T1 T2 0 0 CS20 CS21 CS22 CS10 CS11 CS12 TIMER/COUNTER2 CLOCK SOURCE TCK2 TIMER/COUNTER1 CLOCK SOURCE TCK1 For Timer/Counters 1 and 2, the four different prescaled selections are: CK/8, CK/64, CK/256 and CK/1024 where CK is the CPU clock. Observe that CPU clock frequency can be lower than the XTAL frequency if the XTAL divider is enabled.
The clock source for Timer/Counter0 prescaler is named PCK0. PCK0 is by default connected to the main system clock CK. Observe that CPU clock frequency can be lower than the XTAL frequency if the XTAL divider is enabled. By setting the AS0 bit in ASSR, Timer/Counter 0 prescaler is asynchronously clocked from the TOSC1 pin. This enables use of Timer/Counter0 as a Real Time Clock (RTC). A crystal can be connected between the TOSC1 and TOSC2 pins to serve as an independent clock source for Timer/Counter0.
ATmega603/103 Figure 31. Timer/Counter2 Block Diagram CS21 CS20 CS22 CTC2 COM20 PWM2 TOV0 TOV1 T/C2 CONTROL REGISTER (TCCR2) T/C CLEAR T/C CLK SOURCE UP/DOWN 7 OCF0 OCF2A ICF1 0 TIMER/COUNTER2 (TCNT2) OCF2B 7 TOV2 OCF2 TIMER INT. FLAG REGISTER (TIFR) COM21 OCF2 TIMER INT.
Timer/Counter0 Control Register - TCCR0 Bit 7 6 5 4 3 2 1 0 33 ($53) - PWM0 COM01 COM00 CTC0 CS02 CS01 CS00 Read/Write R R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 TCCR0 Timer/Counter2 Control Register - TCCR2 Bit 7 6 5 4 3 2 1 0 $25 ($45) - PWM2 COM21 COM20 CTC2 CS22 CS21 CS20 Read/Write R R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 TCCR2 • Bit 7 - Res: Reserved Bit This bit is a reserved bit in the ATmeg
ATmega603/103 Table 12. Timer/Counter0 Prescale Select CS02 CS01 CS00 Description 0 0 0 Timer/Counter0 is stopped. 0 0 1 PCK0 0 1 0 PCK0/8 0 1 1 PCK0/32 1 0 0 PCK0/64 1 0 1 PCK0/128 1 1 0 PCK0/256 1 1 1 PCK0/1024 Table 13. Timer/Counter2 Prescale Select CS22 CS21 CS20 Description 0 0 0 Timer/Counter2 is stopped.
Timer/Counter0 Output Compare Register - OCR0 Bit 7 6 5 4 3 2 1 0 $31 ($51) MSB LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 3 2 1 0 OCR0 Timer/Counter2 Output Compare Register - OCR2 Bit 7 6 5 4 $23 ($43) MSB LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 OCR2 The output compare registers are 8-bit read/write registers.
ATmega603/103 Figure 32. Effects on Unsynchronized OCR Latching Compare Value changes Counter Value Compare Value PWM Output Synchronized OCR Latch Compare Value changes Counter Value Compare Value PWM Output Glitch Unsynchronized OCR Latch During the time between the write and the latch operation, a read from OCR0 or OCR2 will read the contents of the temporary location.
• Bit 1 - OCR0UB: Output Compare Register0 Update Busy When Timer/Counter0 operates asynchronously and OCR0 is written, this bit becomes set (one). When OCR0 has been updated from the temporary storage register, this bit is cleared (zero) by hardware. A logical zero in this bit indicates that OCR0 is ready to be updated with a new value. • Bit 0 - TCR0UB: Timer/Counter Control Register0 Update Busy When Timer/Counter0 operates asynchronously and TCCR0 is written, this bit becomes set (one).
ATmega603/103 lost after a wake-up from power down, due to the unstable clock signal. The user is advised to wait for at least one second before using Timer/Counter0 after power-up or wake-up from power down. • Description of wake up from power save mode when the timer is clocked asynchronously: When the interrupt condition is met, the wake up process is started on the following cycle of the timer clock, that is, the timer is always advanced by at least one before the processor can read the counter value.
Figure 33. Timer/Counter1 Block Diagram 8 7 CS11 CS10 CS12 CTC1 ICNC1 ICES1 PWM11 T/C1 CONTROL REGISTER B (TCCR1B) PWM10 COM1B1 COM1B0 COM1A1 TOV1 OCF1A OCF1B ICF1 T/C1 CONTROL REGISTER A (TCCR1A) COM1A0 OCF0 TOV0 OCF1A TOV1 ICF1 T/C1 COMPARE T/C1 INPUT MATCHB IRQ CAPTURE IRQ TIMER INT. FLAG REGISTER (TIFR) TIMER INT.
ATmega603/103 If the noise canceler function is enabled, the actual trigger condition for the capture event is monitored over 4 samples, and all 4 must be equal to activate the capture flag. Timer/Counter1 Control Register A - TCCR1A Bit 7 6 5 4 3 2 1 0 COM1A1 COM1A0 COM1B1 COM1B0 - - PWM11 PWM10 Read/Write R/W R/W R/W R/W R R R/W R/W Initial value 0 0 0 0 0 0 0 0 $2F ($4F) TCCR1A • Bits 7..
Timer/Counter1 Control Register B - TCCR1B Bit 7 6 5 4 3 2 1 0 $2E ($4E) ICNC1 ICES1 - - CTC1 CS12 CS11 CS10 Read/Write R/W R/W R R R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 TCCR1B • Bit 7 - ICNC1: Input Capture1 Noise Canceler (4 CKs) When the ICNC1 bit is cleared (zero), the input capture trigger noise canceler function is disabled. The input capture is triggered at the first rising/falling edge sampled on the input capture pin PD4(IC1) as specified.
ATmega603/103 Timer/Counter1 - TCNT1H and TCNT1L Bit 15 $2D ($4D) 14 13 12 11 10 9 TCNT1H $2C ($4C) Read/Write Initial value 8 MSB LSB 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCNT1L This 16-bit register contains the prescaled value of the 16-bit Timer/Counter1.
Timer/Counter1 Output Compare Register - OCR1AH and OCR1AL Bit $2B 15 14 13 12 11 10 9 OCR1AH $2A Read/Write Initial value 8 MSB LSB 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 8 OCR1AL Timer/Counter1 Output Compare Register - OCR1BH and OCR1BL Bit 15 $29 MSB 14 13 12 11 10 OCR1BH $28 Read/Write Initial value LSB 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W
ATmega603/103 Since the Input Capture Register - ICR1 - is a 16-bit register, a temporary register TEMP is used when ICR1 is read to ensure that both bytes are read simultaneously. When the CPU reads the low byte ICR1L, the data is sent to the CPU and the data of the high byte ICR1H is placed in the TEMP register. When the CPU reads the data in the high byte ICR1H, the CPU receives the data in the TEMP register.
Figure 35. Effects on Unsynchronized OCR1 Latching Compare Value changes Counter Value Compare Value PWM Output OC1X Synchronized OCR1X Latch Compare Value changes Counter Value Compare Value PWM Output OC1X Unsynchronized OCR1X Latch Glitch Note: X = A or B During the time between the write and the latch operation, a read from OCR1A or OCR1B will read the contents of the temporary location.
ATmega603/103 Watchdog Timer The Watchdog Timer is clocked from a separate on-chip oscillator. By controlling the Watchdog Timer prescaler, the Watchdog reset interval can be adjusted as shown in Table 22. See characterization data for typical values at other V CC levels. The WDR - Watchdog Reset - instruction resets the Watchdog Timer. From the Watchdog is reset, eight different clock cycle periods can be selected to determine the reset period.
Table 22. Watch Dog Timer Prescale Select Number of WDT Oscillator cycles Typical time-out at Vcc = 3.0V Typical time-out at Vcc = 5.0V 0 16K cycles 47 ms 15 ms 0 1 32K cycles 94 ms 30 ms 0 1 0 64K cycles 0.19 s 60 ms 0 1 1 128K cycles 0.38 s 0.12 s 1 0 0 256K cycles 0.75 s 0,24 s 1 0 1 512K cycles 1.5 s 0.49 s 1 1 0 1,024K cycles 3.0 s 0.97 s 1 1 1 2,048K cycles 6.0 s 1.
ATmega603/103 EEPROM Data Register - EEDR Bit 7 6 5 4 3 2 1 0 $1D ($3D) MSB LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 EEDR • Bits 7..0 - EEDR7..0: EEPROM Data: For the EEPROM write operation, the EEDR register contains the data to be written to the EEPROM in the address given by the EEAR register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR.
The user should poll the EEWE bit before starting the read operation. If a write operation is in progress when new data or address is written to the EEPROM I/O registers, the write operation will be interrupted, and the result is undefined. Prevent EEPROM Corruption During periods of low VCC, the EEPROM data can be corrupted because the supply voltage is too low for the CPU and the EEPROM to operate properly.
ATmega603/103 Figure 37. SPI Block Diagram The interconnection between master and slave CPUs with SPI is shown in Figure 38. The PB1(SCK) pin is the clock output in the master mode and is the clock input in the slave mode. Writing to the SPI data register of the master CPU starts the SPI clock generator, and the data written shifts out of the PB2(MOSI) pin and into the PB2 (MOSI) pin of the slave CPU. After shifting one byte, the SPI clock generator stops, setting the end of transmission flag (SPIF).
Figure 38. SPI Master-Slave Interconnection MSB MASTER LSB MSB MISO MISO 8 BIT SHIFT REGISTER SLAVE LSB 8 BIT SHIFT REGISTER MOSI MOSI SPI CLOCK GENERATOR SCK SS SCK SS VCC The system is single buffered in the transmit direction and double buffered in the receive direction. This means that characters to be transmitted cannot be written to the SPI Data Register before the entire shift cycle is completed.
ATmega603/103 Data Modes There are four combinations of SCK phase and polarity with respect to serial data, which are determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Figure 39 and Figure 40. Figure 39.
• Bit 4 - MSTR: Master/Slave Select This bit selects Master SPI mode when set (one), and Slave SPI mode when cleared (zero). If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI master mode. • Bit 3 - CPOL: Clock Polarity When this bit is set (one), SCK is high when idle. When CPOL is cleared (zero), SCK is low when idle. Refer to Figure 39 and Figure 40 for additional information.
ATmega603/103 UART The ATmega603/103 features a full duplex (separate receive and transmit registers) Universal Asynchronous Receiver and Transmitter (UART).
Figure 41.
ATmega603/103 Data Reception Figure 42. UART Receiver DATA BUS XTAL BAUD RATE GENERATOR BAUD X 16 UART I/O DATA REGISTER (UDR) BAUD /16 STORE UDR PIN CONTROL LOGIC 10(11)-BIT RX SHIFT REGISTER RXEN TXEN CHR9 RXB8 TXB8 RXC TXC UDRE FE DOR DATA RECOVERY LOGIC RXD UART STATUS REGISTER (USR) RXCIE TXCIE UDRIE RXC UART CONTROL REGISTER (UCR) DATA BUS RXC IRQ The receiver front-end logic samples the signal on the RXD pin at a frequency 16 times the baud rate.
When the stop bit enters the receiver, the majority of the three samples must be one to accept the stop bit. If two or more samples are logical zeros, the Framing Error (FE) flag in the UART Status Register (USR) is set when the received byte is transferred to UDR. Before reading the UDR register, the user should always check the FE bit to detect Framing Errors. FE is cleared when UDR is read.
ATmega603/103 When the TXCIE bit in UCR is set, setting of TXC causes the UART Transmit Complete interrupt to be executed. TXC is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the TXC bit is cleared (zero) by writing a logical one to the bit. • Bit 5 - UDRE: UART Data Register Empty This bit is set (one) when a character written to UDR is transferred to the Transmit shift register.
• Bit 0 - TXB8: Transmit Data Bit 8 When CHR9 is set (one), TXB8 is the 9th data bit in the character to be transmitted.
ATmega603/103 UART Baud Rate Register - UBRR Bit 7 6 5 4 3 2 1 0 $09 ($29) MSB LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 UBRR The UBRR is an 8-bit read/write register which specifies the UART Baud Rate according to the description on the previous page. Analog Comparator The analog comparator compares the input values on the positive input PE2 (AC+) and negative input PE3 (AC-).
• Bit 4 - ACI: Analog Comparator Interrupt Flag This bit is set (one) when a comparator output event triggers the interrupt mode defined by ACI1 and ACI0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set (one) and the I-bit in SREG is set (one). ACI is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.
ATmega603/103 An external reference voltage must be applied to the AREF pin. This voltage must be in the range AGND - AVCC. Figure 45.
Prescaling Figure 46. ADC Prescaler Reset ADEN 7-BIT ADC PRESCALER CK/64 CK/128 CK/32 CK/8 CK/16 CK/4 CK/2 CK ADPS0 ADPS1 ADPS2 ADC CLOCK SOURCE The ADC contains a prescaler, which divides the system clock to an acceptable ADC clock frequency. The ADC accepts input clock frequencies in the range 50 - 200 kHz. Applying a higher input frequency will result in a poorer accuracy, see “ADC DC Characteristics” on page 72.
ATmega603/103 Table 27. ADC Conversion Time Condition Sample Cycle Number Result Ready (cycle number) Total Conversion Time (cycles) Total Conversion Time (µs) 1st Conversion 14 26 28 140 - 560 Single Conversion 1 13 15 75 - 300 Figure 48.
ADC Control and Status Register - ADCSR Bit 7 6 5 4 3 2 1 0 ADEN ADSC - ADIF ADIE ADPS2 ADPS1 ADPS0 Read/Write R/W R/W R R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 $06 ($26) ADCSR • Bit 7 - ADEN: ADC Enable Writing a logical ‘1’ to this bit enables the ADC. By clearing this bit to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion.
ATmega603/103 ADC Data Register - ADCL and ADCH Bit 15 14 13 12 11 10 9 8 $05 ($25) - - - - - - ADC9 ADC8 ADCH $04 ($24) ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 ADCL 7 6 5 4 3 2 1 0 R R R R R R R R R R R R R R R R Read/Write Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 When an ADC conversion is complete, the result is found in these two registers. It is essential that both registers are read, and that ADCL is read before ADCH.
ADC DC Characteristics TA=-40°C to 85°C Symbol Parameter Condition Min Typ Resolution Units 10 Bits Absolute accuracy VREF = 4V, VCC = 4V ADC clock = 200 kHz 1 Absolute accuracy VREF = 4V, VCC = 4V ADC clock = 1 MHz 4 LSB Absolute accuracy VREF = 4V, VCC = 4V ADC clock = 2 MHz 16 LSB Integral Non-Linearity VREF > 2V 0.5 LSB Differential Non-Linearity VREF > 2V 0.
ATmega603/103 For details in the timing for the SRAM interface, please refer to Figure 78, Table 46, Table 47, Table 48, and Table 49 in section “DC Characteristics” on page 105. Figure 50. External SRAM connected to the AVR D[7:0] Port A D ALE G A[7:0] Q SRAM AVR A[15:8] Port C RD RD WR WR Figure 51. External SRAM Access Cycle without wait states T1 T2 T3 System Clock Ø ALE Prev. Address Address Address Data Address Write Data / Address [7..0] Prev.
Figure 52. External SRAM Access Cycle with wait state T1 T2 T3 T4 System Clock Ø ALE Prev. Address Address Address Data Addr. Write Data / Address [7..0] Prev. Address Addr. Read Address [15..8] WR Data / Address [7..0] Prev. Address Address Data RD I/O-Ports All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports.
ATmega603/103 Port A Data Register - PORTA Bit 7 6 5 4 3 2 1 0 $1B ($3B) PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 PORTA Port A Data Direction Register - DDRA Bit 7 6 5 4 3 2 1 0 $1A ($3A) DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 DDRA Port A Input Pins Address - PINA Bit $19 ($3
Figure 53. Port A Schematic Diagrams (Pins PA0 - PA7) RD MOS PULLUP RESET Q R D DDAn C DATA BUS WD RESET R Q D PORTAn PAn C RL An Dn W R SRE WP RP WP: WD: RL: RP: RD: SRE: A: D: W: R: n: WRITE PORTA WRITE DDRA READ PORTA LATCH READ PORTA PIN READ DDRA EXT. SRAM ENABLE ADDRESS DATA WRITE READ 0-7 SRE R W Dn An Port B Port B is an 8-bit bi-directional I/O port with internal pull-ups.
ATmega603/103 The Port B pins with alternate functions are shown in the following table: Table 30.
Table 31. DDBn Effects on Port B Pins DDBn PORTBn I/O Pull up 0 0 Input No Tri-state (Hi-Z) 0 1 Input Yes PBn will source current if ext. pulled low 1 0 Output No Push-Pull Zero Output 1 1 Output No Push-Pull One Output Note: Comment n: 7,6...0, pin number Alternate Functions of Port B The alternate pin configuration is as follows: • OC2/PWM2, Bit 7 OC2/PWM2, Output Compare output for Timer/Counter2 or PWM output when Timer/Counter2 is in PWM Mode.
ATmega603/103 Port B Schematics Note that all port pins are synchronized. The synchronization latches are however, not shown in the figures. Figure 54. Port B Schematic Diagram (Pin PB0) Figure 55.
Figure 56. Port B Schematic Diagram (Pin PB2) Figure 57.
ATmega603/103 Figure 58. Port B Schematic Diagram (Pin PB4) RD MOS PULLUP RESET Q R D DDB4 WD RESET R Q D PORTB4 PB4 DATA BUS C C RL WP RP WP: WD: RL: RP: RD: COM01 COM01 WRITE PORTB WRITE DDRB READ PORTB LATCH READ PORTB PIN READ DDRB OUTPUT MODE SELECT COMP. MATCH 0 Figure 59.
Figure 60. Port B Schematic Diagram (Pin PB7) RD MOS PULLUP RESET R Q D DDB7 C DATA BUS WD RESET R Q D PORTB7 PB7 C RL WP RP WP: WD: RL: RP: RD: COM20 COM21 WRITE PORTB WRITE DDRB READ PORTB LATCH READ PORTB PIN READ DDRB OUTPUT MODE SELECT COMP. MATCH 2 Port C PORT C is an 8-bit Output port. The Port C pins have alternate functions related to the optional external data SRAM.
ATmega603/103 Port C Schematics DATA BUS Figure 61. Port C Schematic Diagram (Pins PC0 - PC7) RESET R Q D PORTCn PCn C RL WP: RL: A: SRE: n: WP WRITE PORTC READ PORTC LATCH SRAM ADDRESS EXTERNAL SRAM ENABLE 0-7 SRE An Port D Port D is an 8 bit bi-directional I/O port with internal pull-up resistors. Three I/O memory address locations are allocated for the Port D, one each for the Data Register - PORTD, $12($32), Data Direction Register - DDRD, $11($31) and the Port D Input Pins - PIND, $10($30).
Port D Data Direction Register - DDRD Bit 7 6 5 4 3 2 1 0 $11 DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 DDRD Port D Input Pins Address - PIND Bit 7 6 5 4 3 2 1 0 $10 PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 Read/Write R R R R R R R R Initial value Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z PIND The Port D Input Pins address - PIND - is not a register, and this
ATmega603/103 Port D Schematics Note that all port pins are synchronized. The synchronization latches are however, not shown in the figures. Figure 62. Port D Schematic Diagram (Pins PD0, PD1, PD2 and PD3) RD MOS PULLUP RESET R Q D DDDn WD RESET R Q D PORTDn PDn DATA BUS C C RL WP RP WP: WD: RL: RP: RD: n: WRITE PORTD WRITE DDRD READ PORTD LATCH READ PORTD PIN READ DDRD 0, 1, 2, 3 INTn Figure 63.
Figure 64. Port D Schematic Diagram (Pin PD5) RD MOS PULLUP RESET Q R D DDD5 WD RESET R Q D PORTD5 PD5 DATA BUS C C RL WP RP WP: WD: RL: RP: RD: WRITE PORTD WRITE DDRD READ PORTD LATCH READ PORTD PIN READ DDRD Figure 65.
ATmega603/103 Port E Port E is an 8-bit bi-directional I/O port with internal pull-up resistors. Three I/O memory address locations are allocated for the Port E, one each for the Data Register - PORTE, $03($23), Data Direction Register - DDRE, $02($22) and the Port E Input Pins - PINE, $01($21). The Port E Input Pins address is read only, while the Data Register and the Data Direction Register are read/write. The Port E output buffers can sink 20 mA.
Port E as general digital I/O PEn, General I/O pin: The DDEn bit in the DDRE register selects the direction of this pin. If DDEn is set (one), PEn is configured as an output pin. If DDEn is cleared (zero), PEn is configured as an input pin. If PEn is set (one) when configured as an input pin, the MOS pull up resistor is activated. To switch the pull up resistor off the PEn has to be cleared (zero) or the pin has to be configured as an output pin.
ATmega603/103 Figure 66. Port E Schematic Diagram, Pin PE0 Figure 67.
Figure 68. Port E Schematic Diagram (Pin PE2) RD MOS PULLUP RESET Q D DDE2 WD RESET Q D PORTE2 C PE2 RL DATA BUS C WP RP AC+ TO COMPARATOR WP: WD: RL: RP: RD: WRITE PORTE WRITE DDRE READ PORTE LATCH READ PORTE PIN READ DDRE Figure 69.
ATmega603/103 Figure 70. Port E Schematic Diagram (Pins PE4, PE5, PE6 and PE7) RD MOS PULLUP RESET Q R D DDEn C DATA BUS WD RESET R Q D PORTEn PEn C RL WP RP WP: WD: RL: RP: RD: n: WRITE PORTE WRITE DDRE READ PORTE LATCH READ PORTE PIN READ DDRE 4, 5, 6, 7 SENSE CONTROL ISCn1 INTn ISCn0 Port F Port F is an 8-bit input port. One I/O memory location is allocated for Port F, the Port F Input Pins - PINF, $00 ($20).
Figure 71. Port F Schematic Diagram (Pins PF7 - PF0) DATA BUS RP PFn TO ADC MUX RP: n: AINn READ PORTF PIN 0-7 Memory Programming Program and Data Memory Lock Bits The ATmega603/103 MCU provides two Lock bits which can be left unprogrammed (‘1’) or can be programmed (‘0’) to obtain the additional features listed in Table 36. The Lock bits can only be erased to ‘1’ with the Chip Erase command.. Table 36.
ATmega603/103 Signature Bytes All Atmel microcontrollers have a three-byte signature code which identifies the device. This code can be read in both serial and parallel mode. The three bytes reside in a separate address space. For the ATmega603 they are: 1. $000: $1E (indicates manufactured by Atmel) 2. $001: $96 (indicates 64 Kb Flash memory) 3. $002: $01 (indicates ATmega603 when signature byte $001 is $96) For the ATmega103 they are: 1. $000: $1E (indicates manufactured by Atmel) 2.
Figure 72. Parallel Programming ATmega603(L), ATmega103(L) RDY/BSY PD1 VCC OE PD2 PB7 - PB0 WR PD3 BS1 PD4 XA0 PD5 XA1 PD6 PAGEL PA0 +12V +5V DATA RESET PD7 XTAL1 GND . Table 38.
ATmega603/103 Table 40. Command Byte Bit Coding Command Byte Command Executed 1000 0000 Chip Erase 0100 0000 Write Fuse Bits 0010 0000 Write Lock Bits 0001 0000 Write Flash 0001 0001 Write EEPROM 0000 1000 Read Signature Bytes 0000 0100 Read Lock and Fuse Bits 0000 0010 Read Flash 0000 0011 Read EEPROM Enter Programming Mode The following algorithm puts the device in parallel programming mode: 1. Apply supply voltage according to Table 37, between VCC and GND. 2.
Programming The Flash The Flash is organized as 256/512 pages of 256 bytes each. When programming the Flash, the program data is latched into a page buffer. This allows one page of program data to be programmed simultaneously. The following procedure describes how to program the entire Flash memory: A: Load Command “Write Flash” 1. Set XA1, XA0 to ‘10’. This enables command loading. 2. Set BS1 to ‘0’ 3. Set DATA to ‘0001 0000’. This is the command for Write Flash. 4. Give XTAL1 a positive pulse.
ATmega603/103 K: Repeat A through J 256/512 times or until all data have been programmed. Figure 73. Programming the Flash waveforms DATA $10 ADDR. LOW ADDR. HIGH DATA LOW XA1 XA2 BS1 XTAL1 WR RDY/BSY RESET +12V OE BS2 PAGEL Figure 74.
Programming The EEPROM The programming algorithm for the EEPROM data memory is as follows (refer to Programming the Flash for details on Command, Address and Data loading): 1. A: Load Command ‘0001 0001’. 2. H: Load Address High Byte ($00-$07/$0F) 3. B: Load Address Low Byte ($00 - $FF) 4. E: Load Data Low Byte ($00 - $FF) L: Write Data Low Byte 1. Set BS to ‘0’. This selects low data. 2. Give WR a negative pulse. This starts programming of the data byte. RDY/BSY goes low. 3.
ATmega603/103 Reading The Flash The algorithm for reading the Flash memory is as follows (refer to Programming the Flash for details on Command and Address loading): 1. A: Load Command ‘0000 0010’. 2. H: Load Address High Byte ($00-$7F/$FF) 3. B: Load Address Low Byte ($00 - $FF) 4. Set OE to ‘0’, and BS1 to ‘0’. The Flash word low byte can now be read at DATA 5. Set BS to ‘1’. The Flash word high byte can now be read at DATA 6. Set OE to ‘1’.
Reading the Fuse and Lock Bits The algorithm for reading the Fuse and Lock bits is as follows (refer to Programming the Flash for details on Command loading): 1. A: Load Command ‘0000 0100’. 2. Set OE to ‘0’, and BS to ‘0’. The status of the Fuse bits can now be read at DATA (‘0’ means programmed). Bit 5 = SPIEN Fuse bit Bit 3 = EESAVE Fuse bit Bit 1 = SUT1 Fuse bit Bit 0 = SUT0 Fuse bit Set OE to ‘0’, and BS to ‘1’. The status of the Lock bits can now be read at DATA (‘0’ means programmed).
ATmega603/103 Table 42. Parallel Programming Characteristics TA = 25°C ± 10%, VCC =5V ± 10% Symbol Parameter Min VPP Programming Enable Voltage 11.
Serial Downloading Both the Flash and EEPROM memory arrays can be programmed using the serial interface while RESET is pulled to GND, or when PEN is low during Power-On Reset. The serial interface consists of pins SCK, RXD/PDI (input) and TXD/PDO (output). After RESET is set low, the Programming Enable instruction needs to be executed first before program/erase instructions can be executed.
ATmega603/103 7. Any memory location can be verified by using the Read instruction which returns the content at the selected address at serial output PE1(PDO/TXD). 8. At the end of the programming session, RESET can be set high to commence normal operation. 9. Power-off sequence (if needed): Set XTAL1 to ‘0’ (if a crystal is not used). Set RESET to ‘1’. Turn VCC power off Table 43 shows the actual delays used in this section. Please NOTE: The MISO pin is not Hi-Z during serial programming.
Table 45. Serial Programming Instruction Set Instruction Instruction Format Programming Enable Chip Erase Operation Byte 1 Byte 2 Byte 3 Byte 4 1010 1100 0101 0011 xxxx xxxx xxxx xxxx Enable Serial Programming while RESET is low. 1010 1100 100x xxxx xxxx xxxx xxxx xxxx Chip Erase EEPROM and Flash. 0010 H000 aaaa aaaa bbbb bbbb oooo oooo Read H(high or low) data o from Program memory at word address a:b.
ATmega603/103 Figure 77. Serial Programming Waveforms SERIAL DATA INPUT PE0(PDI/RXD) MSB LSB SERIAL DATA OUTPUT PE1(PDO/TXD) MSB LSB SERIAL CLOCK INPUT PB1(SCK) SAMPLE Electrical Characteristics Absolute Maximum Ratings* Operating Temperature.................................. -40°C to +105°C *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
DC Characteristics (Continued) TA = -40°C to 85°C VCC = 2.7V to 3.6V and 4.0V to 5.5V (unless otherwise noted) (Continued) Symbol Parameter RRST Reset Pullup RI/O I/O Pin Pullup ICC Power Supply Current Condition Min Typ Max Units 100 500 kΩ 35 120 kΩ Active 4 MHz, VCC = 3V 5.0 mA Idle 4 MHz, VCC = 3V 2.0 mA Power Down , VCC = 3V WDT Enabled 40.0 µA Power Down(5), VCC = 3V WDT Disabled 25.0 µA Power Save(5), VCC = 3V WDT Disabled 35.
ATmega603/103 External Data Memory Timing Table 46. External Data Memory Characteristics, 4.0 - 6.0 Volts, No Wait State 6 MHz Oscillator 0 Symbol Parameter 1/tCLCL Oscillator Frequency Min Variable Oscillator Max Min 0.0 Max Unit 6.0 MHz (1) ns 1 tLHLL ALE Pulse Width 48.3 0.5tCLCL-35.0 2 tAVLL Address Valid A to ALE Low 43.3 0.5tCLCL-40.0(1) ns 3a tLLAX_ST Address Hold After ALE Low, ST/STD/STS Instructions 77.3 0.5tCLCL-10.
Table 48. External Data Memory Characteristics, 2.7 - 3.6 Volts, No Wait State 4 MHz Oscillator 0 1 Symbol Parameter 1/tCLCL Oscillator Frequency tLHLL ALE Pulse Width Min Variable Oscillator Max Min 0.0 65.0 Max Unit 4.0 MHz 0.5tCLCL-60.0 (1) ns (1) ns 2 tAVLL Address Valid A to ALE Low 75.0 0.5tCLCL-50.0 3a tLLAX_ST Address Hold After ALE Low, ST/STD/STS Instructions 125.0 0.5tCLCL(2) 3b tLLAX_LD Address Hold after ALE Low, LD/LDD/LDS Instructions 15.0 15.
ATmega603/103 Figure 78. External RAM Timing T1 T2 T3 T4 0 System Clock O 1 4 7 Address [15..8] Prev. Address Address Data / Address [7..0] Prev. Address 13 15 Data Address 3a WR 16 6 Prev. Address Address Data 5 10 RD Addr. 11 3b Data / Address [7..0] Addr. 14 Write 2 Read ALE 9 8 12 Note: Clock cycle T3 is only present when external SRAM waitstate is enabled External Clock Drive Waveforms Figure 79. External Clock Drive Waveforms VIH1 VIL1 Table 50.
Typical characteristics The following charts show typical behavior. These data are characterized, but not tested. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. All pins on Port F pulled high externally. A sine wave generator with rail to rail output is used as clock source. The power consumption in power-down mode is independent of clock selection.
ATmega603/103 Figure 81. Active Supply Current vs. VCC ACTIVE SUPPLY CURRENT vs. Vcc FREQUENCY = 4 MHz 25 20 TA = 25˚C I cc(mA) TA = 85˚C 15 10 5 0 2 2.5 3 3.5 4 4.5 5 5.5 6 Vcc(V) Figure 82. Idle Supply Current vs. Frequency IDLE SUPPLY CURRENT vs. FREQUENCY TA= 25˚C 18 Vcc= 6V 16 Vcc= 5.5V 14 Vcc= 5V I cc(mA) 12 Vcc= 4.5V 10 Vcc= 4V 8 Vcc= 3.6V 6 Vcc= 3.3V Vcc= 3.0V 4 Vcc= 2.
Figure 83. Idle Supply Current vs. VCC IDLE SUPPLY CURRENT vs. Vcc FREQUENCY = 4 MHz 7 6 TA = 85˚C 5 I cc(mA) TA = 25˚C 4 3 2 1 0 2 2.5 3 3.5 4 4.5 5 5.5 6 Vcc(V) Figure 84. Power Down Supply Current vs. VCC POWER DOWN SUPPLY CURRENT vs. Vcc WATCHDOG TIMER DISABLED 70 TA = 85˚C 60 I cc(µΑ) 50 40 TA = 70˚C 30 20 TA = 45˚C TA = 25˚C 10 0 2 2.5 3 3.5 4 Vcc(V) 112 ATmega603/103 4.5 5 5.
ATmega603/103 Figure 85. Power Down Supply Current vs. VCC POWER DOWN SUPPLY CURRENT vs. Vcc WATCHDOG TIMER ENABLED 250 200 I cc(µΑ) TA = 85˚C 150 TA = 25˚C 100 50 0 2 2.5 3 3.5 4 4.5 5 5.5 6 Vcc(V) Figure 86. Power Save Supply Current vs. VCC POWER SAVE SUPPLY CURRENT vs. Vcc WATCHDOG TIMER DISABLED 80 TA = 85˚C 70 60 I cc(µΑ) 50 40 30 TA = 25˚C 20 10 0 2 2.5 3 3.5 4 4.5 5 5.
Figure 87. Analog Comparator Current vs. VCC ANALOG COMPARATOR CURRENT vs. Vcc 0.9 0.8 0.7 TA = 25˚C 0.6 I cc(mA) TA = 85˚C 0.5 0.4 0.3 0.2 0.1 0 2 2.5 3 3.5 4 4.5 5 5.5 6 Vcc(V) Analog comparator offset voltage is measured as absolute offset Figure 88. Analog Comparator Offset Voltage vs. Common Mode Voltage ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE Vcc = 5V 18 16 TA = 25˚C Offset Voltage (mV) 14 12 TA = 85˚C 10 8 6 4 2 0 0 0.5 1 1.5 2 2.
ATmega603/103 Figure 89. Analog Comparator Offset Voltage vs. Common Mode Voltage ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE Vcc = 2.7V 10 TA = 25˚C Offset Voltage (mV) 8 6 TA = 85˚C 4 2 0 0 0.5 1 1.5 2 2.5 3 Common Mode Voltage (V) Figure 90. Analog Comparator Input Leakage Current ANALOG COMPARATOR INPUT LEAKAGE CURRENT VCC = 6V TA = 25˚C 60 50 30 I ACLK (nA) 40 20 10 0 -10 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.
Figure 91. Watchdog Oscillator Frequency vs. VCC WATCHDOG OSCILLATOR FREQUENCY vs. Vcc 1600 TA = 25˚C 1400 TA = 85˚C F RC (KHz) 1200 1000 800 600 400 200 0 2 2.5 3 3.5 4 4.5 5 5.5 6 Vcc (V) Sink and source capabilities of I/O ports are measured on one pin at a time. Figure 92. Pull-Up Resistor Current vs. Input Voltage PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE Vcc = 5V 120 TA = 25˚C 100 TA = 85˚C I OP (µA) 80 60 40 20 0 0 0.5 1 1.5 2 2.
ATmega603/103 Figure 93. Pull-Up Resistor Current vs. Input Voltage PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE Vcc = 2.7V 30 TA = 25˚C 25 TA = 85˚C 15 I OP (µA) 20 10 5 0 0 0.5 1 1.5 2 2.5 3 VOP (V) Figure 94. I/O Pin Sink Current vs. Output Voltage I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 5V 70 TA = 25˚C 60 TA = 85˚C 50 30 I OL (mA) 40 20 10 0 0 0.5 1 1.5 2 2.
Figure 95. I/O Pin Source Current vs. Output Voltage I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 5V 20 TA = 25˚C 18 16 TA = 85˚C 14 I OH (mA) 12 10 8 6 4 2 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VOH (V) Figure 96. I/O Pin Sink Current vs. Output Voltage I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 2.7V 25 TA = 25˚C 20 TA = 85˚C 10 I OL (mA) 15 5 0 0 0.5 1 VOL (V) 118 ATmega603/103 1.
ATmega603/103 Figure 97. I/O Pin Source Current vs. Output Voltage I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 2.7V 6 TA = 25˚C 5 TA = 85˚C 3 I OH (mA) 4 2 1 0 0 0.5 1 1.5 2 2.5 3 VOH (V) Figure 98. I/O Pin Input Threshold Voltage vs. VCC I/O PIN INPUT THRESHOLD VOLTAGE vs. Vcc TA = 25˚C 2.5 Threshold Voltage (V) 2 1.5 1 0.5 0 2.7 4.0 5.
Figure 99. I/O Pin Input Hysteresis vs. VCC I/O PIN INPUT HYSTERESIS vs. Vcc TA = 25˚C 0.18 0.16 Input hysteresis (V) 0.14 0.12 0.1 0.08 0.06 0.04 0.02 0 2.7 4.0 Vcc 120 ATmega603/103 5.
ATmega603/103 Register Summary Address Name $3F ($5F) SREG Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Page I T H S V N Z C page 21 page 21 $3E ($5E) SPH SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 $3D ($5D) SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 page 21 $3C ($5C) XDIV XDIVEN XDIV6 XDIV5 XDIV4 XDIV3 XDIV2 XDIV1 XDIV0 page 23 page 22 $3B ($5B) RAMPZ $3A ($5A) EICR $39 ($59) EIMSK - - - - - - - RAMPZ0 ISC71 ISC70 ISC61 ISC60 ISC51 ISC50 ISC41 ISC40
Instruction Set Summary Mnemonics Operands Description Operation Flags #Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers ADC Rd, Rr Add with Carry two Registers ADIW Rdl,K Add Immediate to Word SUB Rd, Rr Subtract two Registers SUBI Rd, K Subtract Constant from Register SBC Rd, Rr SBCI Rd, K SBIW Rdl,K Subtract Immediate from Word AND Rd, Rr Logical AND Registers ANDI Rd, K Logical AND Register and Constant OR Rd, Rr Logical OR Registers ORI Rd, K
ATmega603/103 Instruction Set Summary (Continued) Mnemonics Operands Description Operation Flags #Clocks R0 ← (Z+RAMPZ) None 3 DATA TRANSFER INSTRUCTIONS ELPM(1) Extended Load Program Memory MOV Rd, Rr Move Between Registers LDI Rd, K Load Immediate LD Rd, X Load Indirect LD Rd, X+ Load Indirect and Post-Inc. LD Rd, - X Load Indirect and Pre-Dec. LD Rd, Y Load Indirect LD Rd, Y+ Load Indirect and Post-Inc. LD Rd, - Y Load Indirect and Pre-Dec.
Ordering Information Speed (MHz) Power Supply 4 2.7 - 3.6V 6 4 6 4.0 - 5.5V 2.7 - 3.6V 4.0 - 5.
ATmega603/103 Packaging Information 64A, 64-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP) Dimensions in Millimeters and (Inches)* 16.25(0.640) SQ 15.75(0.620) PIN 1 ID 0.45(0.018) 0.30(0.012) 0.80(0.031) BSC 14.10(0.555) SQ 13.90(0.547) 0.20(0.008) 0.10(0.004) 1.20 (.047) MAX 0-7 0.75(0.030) 0.45(0.018) 0.15(0.006) 0.05(0.
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