Instruction Manual

1
Features
• Industry-standard Architecture
– Emulates Many 24-pin PALs
®
– Low-cost Easy-to-use Software Tools
• High-speed Electrically-erasable Programmable Logic Devices
– 7.5 ns Maximum Pin-to-pin Delay
• Several Power Saving Options
• CMOS and TTL Compatible Inputs and Outputs
• Input and I/O Pull-up Resistors
• Advanced Flash Technology
– Reprogrammable
– 100% Tested
• High-reliability CMOS Process
– 20 Year Data Retention
– 100 Erase/Write Cycles
– 2,000V ESD Protection
– 200 mA Latchup Immunity
• Commercial and Industrial Temperature Ranges
• Dual-in-line and Surface Mount Packages in Standard Pinouts
• PCI-Compliant
Block Diagram
Device I
CC
, Standby I
CC
, Active
ATF20V8B 50 mA 55 mA
ATF20V8BQ 35 mA 40 mA
ATF20V8BQL 5 mA 20 mA
High-
performance
EE PLD
ATF20V8B
ATF20V8BQ
ATF20V8BQL
Rev. 0407H–04/01
Pin Configurations
All Pinouts Top View
Pin Name Function
CLK Clock
I Logic Inputs
I/O Bi-directional Buffers
OE Output Enable
* No Internal Connection
VCC +5V Supply
TSSOP
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
CLK/IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
GND
VCC
IN
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IN
OE/IN
DIP/SOIC
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
CLK/IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
GND
VCC
IN
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IN
OE/IN
PLCC
5
6
7
8
9
10
11
25
24
23
22
21
20
19
IN
IN
IN
*
IN
IN
IN
I/O
I/O
I/O
*
I/O
I/O
I/O
4 3 2 1
28 27 26
12 13 14 15 16 17 18
IN IN
GND
*
OE/IN
IN
I/O
IN IN CLK/IN * VCC IN I/O