Features • Industry-standard Architecture – Emulates Many 20-pin PALs® – Low-cost Easy-to-use Software Tools High-speed Electrically-erasable Programmable Logic Devices – 5 ns Maximum Pin-to-pin Delay Low-power - 100 µA Pin-controlled Power-down Mode Option CMOS and TTL Compatible Inputs and Outputs – I/O Pin Keeper Circuits Advanced Flash Technology – Reprogrammable – 100% Tested High-reliability CMOS Process – 20 Year Data Retention – 100 Erase/Write Cycles – 2,000V ESD Protection – 200 mA Latchup Immunit
Description The ATF16V8C is a high-performance EECMOS Programmable Logic Device that utilizes Atmel’s proven electricallyerasable Flash memory technology. Speeds down to 5 ns and a 100 µA pin-controlled power-down mode option are offered. All speed ranges are specified over the full 5V ± 10% range for industrial temperature ranges; 5V ± 5% for commercial range 5-volt devices.
ATF16V8C DC Characteristics Symbol Parameter Condition IIL Input or I/O Low Leakage Current IIH Max Units 0 ≤ VIN ≤ VIL (Max) -10.0 µA Input or I/O High Leakage Current 3.5 ≤ VIN ≤ VCC 10.0 µA ICC1(1) 15 MHz, VCC = Max, VIN = 0, VCC, Outputs Open Com. 115 mA Power Supply Current, Standby Ind. 130 mA IPD Power Supply Current, Power-down Mode IOS Output Short Circuit Current VOUT = 0.
AC Characteristics -5 -7 Symbol Parameter tPD Input or Feedback to Non-Registered Output tCF Clock to Feedback tCO Clock to Output 1 tS Input or Feedback Setup Time 3 5 ns tH Input Hold Time 0 0 ns tP Clock Period 6 8 ns tW Clock Width 3 4 ns FMAX Min Max Min Max Units 1 5 3 7.
ATF16V8C Input Test Waveforms and Measurement Levels: Output Test Loads: 5.0V R1 = 200 OUTPUT PIN R2 = 200 CL = 50 pF tR, tF < 1.5 ns (10% to 90%) Pin Capacitance(1) f = 1 MHz, T = 25°C CIN COUT Note: Typ Max Units Conditions 5 8 pF VIN = 0V 6 8 pF VOUT = 0V 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested. Power-up Reset The ATF16V8C’s registers are designed to reset during power-up.
Power-down Mode The ATF16V8C includes an optional pin controlled powerdown feature. Device pin 4 may be configured as the power-down pin. When this feature is enabled and the power-down pin is high, total current consumption drops to less than 100 µA. In the power-down mode, all output data and internal logic states are latched and held. All registered and combinatorial output data remains valid. Any outputs which were in a HI-Z state at the onset of power-down will remain at HI-Z.
ATF16V8C Functional Logic Diagram Description The Logic Option and Functional Diagrams describe the ATF16V8C architecture. Eight configurable macrocells can be configured as a registered output, combinatorial I/O, combinatorial output, or dedicated input. The ATF16V8C can be configured in one of three different modes. Each mode makes the ATF16V8C look like a different device. Most PLD compilers can choose the right mode automatically.
Macrocell Configuration Software compilers support the three different OMC modes as different device types. These device types are listed in the table below. Most compilers have the ability to automatically select the device type, generally based on the register usage and output enable (OE) usage. Register usage on the device forces the software to choose the registered mode. All combinatorial outputs with OE controlled by the product term will force the software to choose the complex mode.
ATF16V8C Registered Mode Logic Diagram * Input not available if power-down mode is enabled.
ATF16V8C Complex Mode PAL Device Emulation/PAL Replacement In the Complex Mode, combinatorial output and I/O functions are possible. Pins 1 and 11 are regular inputs to the array. Pins 13 through 18 have pin feedback paths back to the AND-array, which makes full I/O capability possible. Pins 12 and 19 (outermost macrocells) are outputs only. They do not have input capability. In this mode, each macrocell has seven product terms going to the sum term and one product term enabling the output.
ATF16V8C Complex Mode Logic Diagram * Input not available if power-down mode is enabled.
Simple Mode Logic Diagram * Input not available if power-down mode is enabled.
ATF16V8C 13
ATF16V8C
ATF16V8C 15
Ordering Information tPD (ns) tS (ns) tCO (ns) Ordering Code Package Operation Range 5 3 4 ATF16V8C-5JC 20J Commercial (0°C to 70°C) 7.
ATF16V8C Packaging Information 20J, 20-lead, Plastic J-leaded Chip Carrier (PLCC) Dimensions in Inches and (Millimeters) 20P3, 20-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) Dimensions in Inches and (Millimeters) 1.060(26.9) .980(24.9) PIN 1 .280(7.11) .240(6.10) .090(2.29) MAX .900(22.86) REF .210(5.33) MAX .005(.127) MIN SEATING PLANE .015(.381) MIN .150(3.81) .115(2.92) .022(.559) .014(.356) .070(1.78) .045(1.13) .110(2.79) .090(2.29) .325(8.26) .300(7.62) 0 REF 15 .014(.356) .008(.
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