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Features

• High-density, High-performance, Electrically-erasable Complex Programmable

Logic Device

– 3.0 to 3.6V Operating Range

– 32 Macrocells

– 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell

–44Pins

– 15nsMaximumPin-to-pinDelay

– Registered Operation up to 77 MHz

– Enhanced Routing Resources

• In-System Programmability (ISP) via JTAG

• Flexible Logic Macrocell

– D/T Latch Configurable Flip-flops

– Global and Individual Register Control Signals

– Global and Individual Output Enable

– Programmable Output Slew Rate

– Programmable Output Open Collector Option

– Maximum Logic Utilization by Burying a Register with a COM Output

• Advanced Power Management Features

– Pin-controlled 0.75 mA Standby Mode

– Programmable Pin-keeper Inputs and I/Os

– Reduced-power Feature per Macrocell

• Available in Commercial and Industrial Temperature Ranges

• Available in 44-lead PLCC and TQFP

• Advanced EEPROM Technology

– 100% Tested

– Completely Reprogrammable

– 10,000 Program/Erase Cycles

– 20-year Data Retention

– 2000V ESD Protection

– 200 mA Latch-up Immunity

• JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported

• PCI-compliant

• Security Fuse Feature

Enhanced Features

• Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)

• Output Enable Product Terms

• D Latch Mode

• Combinatorial Output with Registered Feedback within Any Macrocell

• Three Global Clock Pins

• Fast Registered Input from Product Term

• Programmable “Pin-keeper” Option

• V

Power-up Reset Option

• Pull-up Option on JTAG Pins TMS and TDI

• Advanced Power Management Features

– Individual Macrocell Power Option

High-

performance

EEPROM CPLD

ATF1502ASV

Rev. 1615G–PLD–09/02

Summary of content (22 pages)

PAGE 1
Features • High-density, High-performance, Electrically-erasable Complex Programmable • • • • • • • • • Logic Device – 3.0 to 3.
PAGE 2
44 43 42 41 40 39 38 37 36 35 34 I/O I/O I/O VCC GCLK2/OE2/I GCLR/I I/OE1 GCLK1/I GND GCLK3/I/O I/O 44-lead TQFP Top View 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 I/O I/O/TDO I/O I/O VCC I/O I/O I/O/TCK I/O GND I/O I/O I/O I/O I/O GND VCC I/O PD2/I/O I/O I/O I/O 12 13 14 15 16 17 18 19 20 21 22 I/O/TDI I/O I/O GND PD1/I/O I/O TMS/I/O I/O VCC I/O I/O 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 7 8 9 10 11 12 13 14 15 16 17 I/O I/O/TDO I/O I/O VCC I/O I/O I/O/
PAGE 3
ATF1502ASV Block Diagram B 32 Each of the 32 macrocells generates a buried feedback that goes to the global bus. Each input and I/O pin also feeds into the global bus. The switch matrix in each logic block then selects 40 individual signals from the global bus. Each macrocell also generates a foldback logic term that goes to a regional bus. Cascade logic between macrocells in the ATF1502ASV allows fast, efficient generation of complex logic functions.
PAGE 4
Boundary-scan Description Language (BSDL). ISP allows the device to be programmed without removing it from the printed circuit board. In addition to simplifying the manufacturing flow, ISP also allows design modifications to be made in the field via software. Figure 1. ATF1502ASV Macrocell Product Terms and Select Mux Each ATF1502ASV macrocell has five product terms. Each product term receives as its inputs all signals from both the global bus and regional bus.
PAGE 5
ATF1502ASV Flip-flop The ATF1502ASV’s flip-flop has very flexible data and control functions. The data input can come from either the XOR gate, from a separate product term or directly from the I/O pin. Selecting the separate product term allows creation of a buried registered feedback within a combinatorial output macrocell. (This feature is automatically implemented by the fitter software). In addition to D, T, JK and SR operation, the flip-flop can also be configured as a flow-through latch.
PAGE 6
Input Diagram VCC INPUT 100K ESD PROTECTION CIRCUIT PROGRAMMABLE OPTION I/O Diagram VCC OE I/O DATA VCC 100K PROGRAMMABLE OPTION Speed/Power Management The ATF1502ASV has several built-in speed and power management features. To further reduce power, each ATF1502ASV macrocell has a reduced-power bit feature. To reduce power consumption this feature may be actived (by changing the default value of OFF to ON) for any or all macrocells. The ATF1502ASV also has an optional power-down mode.
PAGE 7
ATF1502ASV All power-down AC characteristic parameters are computed from external input or I/O pins, with reduced-power bit turned on. For macrocells in reduced-power mode (reduced-power bit turned on), the reduced-power adder, tRPA, must be added to the AC parameters, which include the data paths tLAD, tLAC, tIC, tACL, tACH and tSEXP. The ATF1502ASV macrocell also has an option whereby the power can be reduced on a per-macrocell basis.
PAGE 8
When using the ISP hardware or software to program the ATF1502ASV devices, four I/O pins must be reserved for the JTAG interface. However, the logic features that the macrocells have associated with these I/O pins are still available to the design for burned logic functions. To facilitate ISP programming by the Automated Test Equipment (ATE) vendors. Serial Vector Format (SVF) files can be created by Atmel-provided software utilities.
PAGE 9
ATF1502ASV BSC Configuration for Input and I/O Pins (Except JTAG TAP Pins) Dedicated Input To Internal Logic TDO Capture Registers CLOCK SHIFT TDI (From Next Register) Note: BSC Configuration for Macrocells The ATF1502ASV has a pull-up option on TMS and TDI pins. This feature is selected as a design option.
PAGE 10
Power-down Mode The ATF1502ASV includes an optional pin-controlled power-down feature. When this mode is enabled, the PD pin acts as the power-down pin. When the PD pin is high, the device supply current is reduced to less than 3 mA. During power-down, all output data and internal logic states are latched and held. Therefore, all registered and combinatorial output data remain valid. Any outputs that were in a high-Z state at the onset will remain at high-Z.
PAGE 11
ATF1502ASV DC and AC Operating Conditions Operating Temperature (Ambient) VCC (3.3V) Power Supply Commercial Industrial 0°C - 70°C -40°C - 85°C 3.0V ± 3.6% 3.0V ± 3.
PAGE 12
Pin Capacitance(1) Typ Max Units Conditions CIN 8 10 pF VIN = 0V; f = 1.0 MHz CI/O 8 10 pF VOUT = 0V; f = 1.0 MHz Note: 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested. The OGI pin (high-voltage pin during programming) has a maximum capacitance of 12 pF.
PAGE 13
ATF1502ASV AC Characteristics (1) -15 Symbol Parameter tPD1 -20 Min Max Min Max Units Input or Feedback to Non-registered Output 3 15 20 ns tPD2 I/O Input or Feedback to Non-registered Feedback 3 12 16 ns tSU Global Clock Setup Time 11 16 ns tH Global Clock Hold Time 0 0 ns tFSU Global Clock Setup Time of Fast Input 3 3 ns tFH Global Clock Hold Time of Fast Input 1 1.
PAGE 14
AC Characteristics (Continued)(1) -15 Symbol Parameter tZX3 Output Buffer Enable Delay (Slow slew rate = ON; VCCIO = 5.0V/3.
PAGE 15
ATF1502ASV SUPPLY CURRENT VS. SUPPLY VOLTAGE ASV VERSION (T A = 25°C, F = 0) OUTPUT SOURCE CURRENT VS. SUPPLY VOLTAGE (VOH = 2.4V, TA = 25°C) 70 0 60 -2 -4 40 -6 IOH (mA) ICC (mA) STANDARD POWER 50 30 20 -8 -10 -12 REDUCED POWER 10 -14 -16 2.75 0 3 3.1 3.2 3.3 3.4 3.5 3.6 3.00 3.25 3.50 3.75 4.00 SUPPLY VOLTAGE (V) V CC (V) SUPPLY CURRENT VS. SUPPLY VOLTAGE ASVL (LOW-POWER) VERSION (TA = 25°C, F = 0) SUPPLY CURRENT VS.
PAGE 16
OUTPUT SINK CURRENT VS. OUTPUT VOLTAGE (VCC = 3.3V, TA = 25°C) OUTPUT SOURCE CURRENT VS. OUTPUT VOLTAGE (VCC = 3.3V, TA = 25°C) 100 10 0 80 -20 IOL (mA) IOH (mA) -10 -30 -40 60 40 -50 20 -60 -70 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 4.0 0 0.5 1 1.5 2 2.5 3 3.5 4 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) OUTPUT SINK CURRENT VS. SUPPLY VOLTAGE (VOL = 0.5V, TA = 25°C) INPUT CURRENT VS. INPUT VOLTAGE (VCC = 3.3V, TA = 25°C) 40 15 INPUT CURRENT (uA) IOL (mA) 35 30 25 20 2.75 3.
PAGE 17
ATF1502ASV ATF1502ASV Dedicated Pinouts 44-lead TQFP 44-lead J-lead INPUT/OE2/GCLK2 40 2 INPUT/GCLR 39 1 INPUT/OE1 38 44 INPUT/GCLK1 37 43 I/O / GCLK3 35 41 I/O / PD (1,2) 5, 19 11, 25 I/O / TDI (JTAG) 1 7 I/O / TMS (JTAG) 7 13 I/O / TCK (JTAG) 26 32 I/O / TDO (JTAG) 32 38 GND 4, 16, 24, 36 10, 22, 30, 42 VCCI 9, 17, 29, 41 3, 15, 23, 35 # of Signal Pins 36 36 # User I/O Pins 32 32 Dedicated Pin OE (1, 2) Global OE pins GCLR Global Clear pin GCLK (1, 2, 3) G
PAGE 18
ATF1502ASV I/O Pinouts 18 MC PLC 44-lead PLCC 44-lead TQFP 1 A 4 42 2 A 5 43 3 A 6 44 4/TDI A 7 1 5 A 8 2 6 A 9 3 7/PD1 A 11 5 8 A 12 6 9/TMS A 13 7 10 A 14 8 11 A 16 10 12 A 17 11 13 A 18 12 14 A 19 13 15 A 20 14 16 A 21 15 17 B 41 35 18 B 40 34 19 B 39 33 20/TDO B 38 32 21 B 37 31 22 B 36 30 23 B 34 28 24 B 33 27 25/TCK B 32 26 26 B 31 25 27 B 29 23 28 B 28 22 29 B 27 21 30 B 26 20
PAGE 19
ATF1502ASV Ordering Information tPD (ns) tCO1 (ns) fMAX (MHz) 15 8 15 Ordering Code Package 100 ATF1502ASV-15 AC44 ATF1502ASV-15 JC44 44A 44J Commercial (0°C to 70°C) 8 100 ATF1502ASV-15 AI44 ATF1502ASV-15 JI44 44A 44J Industrial (-40°C to +85°C) 20 12 83.3 ATF1502ASV-20 AC44 ATF1502ASV-20 JC44 44A 44J Commercial (0°C to 70°C) 20 12 83.3 ATF1502ASV-20 AI44 ATF1502ASV-20 JI44 44A 44J Industrial (-40°C to +85°C) Note: Operation Range 1. Shaded area indicates preliminary data.
PAGE 20
Packaging Information 44A – TQFP PIN 1 B PIN 1 IDENTIFIER E1 e E D1 D C 0˚~7˚ A1 A2 A L COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. SYMBOL MIN NOM MAX A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.
PAGE 21
ATF1502ASV 44J – PLCC 1.14(0.045) X 45° PIN NO. 1 1.14(0.045) X 45° 0.318(0.0125) 0.191(0.0075) IDENTIFIER E1 D2/E2 B1 E B e A2 D1 A1 D A 0.51(0.020)MAX 45° MAX (3X) COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-018, Variation AC. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side.
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