Manual

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Features

• High-density, High-performance, Electrically-erasable Complex Programmable

Logic Device

– 32 Macrocells

– 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell

–44Pins

– 7.5 ns Maximum Pin-to-pin Delay

– Registered Operation up to 125 MHz

– Enhanced Routing Resources

• In-System Programmability (ISP) via JTAG

• Flexible Logic Macrocell

– D/T Latch Configurable Flip-flops

– Global and Individual Register Control Signals

– Global and Individual Output Enable

– Programmable Output Slew Rate

– Programmable Output Open Collector Option

– Maximum Logic Utilization by Burying a Register with a COM Output

• Advanced Power Management Features

• Automatic10µAStandbyfor“L”Version

• Pin-controlled 1 mA Standby Mode

• Programmable Pin-keeper Inputs and I/Os

• Reduced-power Feature per Macrocell

• Available in Commercial and Industrial Temperature Ranges

• Available in 44-lead PLCC and TQFP

• Advanced EEPROM Technology

– 100% Tested

– Completely Reprogrammable

– 10,000 Program/Erase Cycles

– 20-year Data Retention

– 2000V ESD Protection

– 200 mA Latch-up Immunity

• JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported

• PCI-compliant

• Security Fuse Feature

Enhanced Features

• Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)

• Output Enable Product Terms

• D Latch Mode

• Combinatorial Output with Registered Feedback within Any Macrocell

• Three Global Clock Pins

• ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O

(“L” versions)

• Fast Registered Input from Product Term

• Programmable “Pin-keeper” Option

• V

Power-up Reset Option

• Pull-up Option on JTAG Pins TMS and TDI

• Advanced Power Management Features

– Input Transition Detection

– Power-down (“L” versions)

– Individual Macrocell Power Option

– Disable ITD on Global Clocks, Inputs and I/O

High-

performance

EEPROM CPLD

ATF1502AS

ATF1502ASL

Rev. 0995J–PLD–09/02

Summary of content (25 pages)

PAGE 1
Features • High-density, High-performance, Electrically-erasable Complex Programmable • • • • • • • • • • • • • Logic Device – 32 Macrocells – 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell – 44 Pins – 7.
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44 43 42 41 40 39 38 37 36 35 34 I/O I/O I/O VCC GCLK2/OE2/I GCLR/I I/OE1 GCLK1/I GND GCLK3/I/O I/O 44-lead TQFP Top View 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 I/O I/O/TDO I/O I/O VCC I/O I/O I/O/TCK I/O GND I/O I/O I/O I/O I/O GND VCC I/O PD2/I/O I/O I/O I/O 12 13 14 15 16 17 18 19 20 21 22 I/O/TDI I/O I/O GND PD1/I/O I/O TMS/I/O I/O VCC I/O I/O 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 7 8 9 10 11 12 13 14 15 16 17 I/O I/O/TDO I/O I/O VCC I/O I/O I/O/
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ATF1502AS(L) Block Diagram B 32 Each of the 32 macrocells generates a buried feedback that goes to the global bus. Each input and I/O pin also feeds into the global bus. The switch matrix in each logic block then selects 40 individual signals from the global bus. Each macrocell also generates a foldback logic term that goes to a regional bus. Cascade logic between macrocells in the ATF1502AS allows fast, efficient generation of complex logic functions.
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Figure 1. ATF1502AS Macrocell Product Terms and Select Mux Each ATF1502AS macrocell has five product terms. Each product term receives as its inputs all signals from both the global bus and regional bus. The product term select multiplexer (PTMUX) allocates the five product terms as needed to the macrocell logic gates and control signals. The PTMUX programming is determined by the design compiler, which selects the optimum macrocell configuration.
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ATF1502AS(L) The clock itself can be either one of the Global CLK signals (GCK[0 : 2]) or an individual product term. The flip-flop changes state on the clock’s rising edge. When the GCK signal is used as the clock, one of the macrocell product terms can be selected as a clock enable. When the clock enable function is active and the enable signal (product term) is low, all clock edges are ignored.
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Input Diagram I/O Diagram Speed/Power Management The ATF1502AS has several built-in speed and power management features. The ATF1502AS contains circuitry that automatically puts the device into a low-power standby mode when no logic transitions are occurring. This not only reduces power consumption during inactive periods, but also provides proportional power savings for most applications running at system speeds below 50 MHz. This feature may be selected as a design option.
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ATF1502AS(L) All pin transitions are ignored until the PD pin is brought low. When the power-down feature is enabled, the PD1 or PD2 pin cannot be used as a logic input or output. However, the pin’s macrocell may still be used to generate buried foldback and cascade logic signals. All power-down AC characteristic parameters are computed from external input or I/O pins, with reduced-power bit turned on.
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Atmel provides ISP hardware and software to allow programming of the ATF1502AS via the PC. ISP is performed by using either a download cable, a comparable board tester or a simple microprocessor interface. When using the ISP hardware or software to program the ATF1502AS devices, four I/O pins must be reserved for the JTAG interface. However, the logic features that the macrocells have associated with these I/O pins are still available to the design for burned logic functions.
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ATF1502AS(L) JTAG Boundary-scan Cell (BSC) Testing The ATF1502AS contains up to 32 I/O pins and four input pins, depending on the device type and package type selected. Each input pin and I/O pin has its own boundary-scan cell (BSC) in order to support boundary-scan testing as described in detail by IEEE Standard 1149.1. A typical BSC consists of three capture registers or scan registers and up to two update registers. There are two types of BSCs, one for input or I/O pin, and one for the macrocells.
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The ATF1502AS also supports the growing need in the industry to support the new Peripheral Component Interconnect (PCI) interface standard in PCI-based designs and specifications. The PCI interface calls for high current drivers, which are much larger than the traditional TTL drivers. In general, PLDs and FPGAs parallel outputs to support the high current load required by the PCI interface. The ATF1502AS allows this without contributing to system noise while delivering low output to output skew.
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ATF1502AS(L) PCI DC Characteristics (Preliminary) Symbol Parameter VCC Conditions Min Max Units Supply Voltage 4.75 5.25 V VIH Input High Voltage 2.0 VCC + 0.5 V VIL Input Low Voltage -0.5 0.8 V IIH Input High Leakage Current(1) VIN = 2.7V 70 µA -70 µA (1) IIL Input Low Leakage Current VIN = 0.5V VOH Output High Voltage IOUT = -2 mA VOL Output Low Voltage IOUT = 3 mA, 6 mA CIN 2.4 V 0.
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Power-down Mode The ATF1502AS includes an optional pin-controlled power-down feature. When this mode is enabled, the PD pin acts as the power-down pin. When the PD pin is high, the device supply current is reduced to less than 5 mA. During power-down, all output data and internal logic states are latched and held. Therefore, all registered and combinatorial output data remain valid. Any outputs that were in a high-Z state at the onset will remain at high-Z.
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ATF1502AS(L) DC and AC Operating Conditions Operating Temperature (Ambient) Commercial Industrial 0°C - 70°C -40°C - 85°C 5V ± 5% 5V ± 10% VCC (5V) Power Supply DC Characteristics Symbol Parameter Condition Min IIL Input or I/O Low Leakage Current VIN = V CC IIH Input or I/O High Leakage Current IOZ Tri-state Output Off-state Current VO = V CC or GND ICC1 Power Supply Current, Standby VCC = Max VIN = 0, VCC Std Mode “L” Mode ICC2 Power Supply Current, Power-down Mode VCC = Max VIN
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Pin Capacitance(1) Typ Max Units Conditions CIN 8 10 pF VIN = 0V; f = 1.0 MHz CI/O 8 10 pF VOUT = 0V; f = 1.0 MHz Note: 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested. The OGI pin (high-voltage pin during programming) has a maximum capacitance of 12 pF. Timing Model Input Test Waveforms and Measurement Levels tR, tF = 1.
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ATF1502AS(L) AC Characteristics (1) -7 Min -10 Max Min -15 -25 Symbol Parameter Max Min Max 7.5 10 3 7 9 3 tPD1 Input or Feedback to Non-registered Output tPD2 I/O Input or Feedback to Non-registered Feedback tSU Global Clock Setup Time 6 7 11 20 ns tH Global Clock Hold Time 0 0 0 0 ns tFSU Global Clock Setup Time of Fast Input 3 3 3 5 ns tFH Global Clock Hold Time of Fast Input 0.5 0.
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AC Characteristics (Continued)(1) -7 Min Max Min -25 Parameter tZX3 Output Buffer Enable Delay (Slow slew rate = ON; VCCIO = 5.0V/3.3V; CL = 35 pF) 9 9 tXZ Output Buffer Disable Delay (CL = 5 pF) 4 5 tSU Register Setup Time 3 3 4 6 ns tH Register Hold Time 2 3 4 6 ns tFSU Register Setup Time of Fast Input 3 3 2 3 ns tFH Register Hold Time of Fast Input 0.5 0.
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ATF1502AS(L) SUPPLY CURRENT VS. SUPPLY VOLTAGE (T = 25°C, NON-TURBO, BIT6 = 0, BIT 30 = 0) SUPPLY CURRENT VS. SUPPLY VOLTAGE AS VERSION (TA = 25°C, F = 0) 120.0 70 100.0 60 80.0 ICC (µA) ICC (mA) 50 STANDARD POWER 40 60.0 40.0 30 20 20.0 REDUCED POWER 10 0.0 4.00 4.50 4.75 5.00 0 5.25 5.50 6.00 VCC (V) 4.5 4.75 5 5.25 5.5 VCC (V) SUPPLY CURRENT VS. SUPPLY VOLTAGE PIN-CONTROLLED POWER-DOWN MODE (TA = 25°C, F = 0) 14 12 ICC (mA) 10 8 TBD 6 4 2 0 4.5 4.75 5 5.
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INPUT CLAMP CURRENT VS. INPUT VOLTAGE (VCC = 5V, T A = 25°C) INPUT CURRENT VS. INPUT VOLTAGE (VCC = 5V, T A = 25°C) 40 0 30 20 INPUT CURRENT (mA) INPUT CURRENT (mA) -10 -20 10 -30 -40 0 -10 -50 -20 -60 -1.00 -30 -0.80 -0.60 -0.40 -0.20 0.00 0.0 0.5 1.0 1.5 INPUT VOLTAGE (V) 2.0 2.5 3.0 INPUT VOLTAGE (V) 3.5 4.0 4.5 5.0 OUTPUT SINK CURRENT VS. OUTPUT VOLTAGE (VCC = 5V, TA = 25°C) OUTPUT SINK CURRENT VS. SUPPLY VOLTAGE (VOL = 0.5V, T A = 25°C) 140.0 43 120.0 42 100.
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ATF1502AS(L) NORMALIZED TCO VS. TEMPERATURE (VCC = 5.0V) 1.2 1.2 1.1 1.1 NORMALIZED TCO NORMALIZED TPD NORMALIZED TCO VS. SUPPLY VOLTAGE (TA = 25°C) 1.0 1.0 0.9 0.9 0.8 0.8 4.5 4.8 5.0 5.3 -40.0 5.5 0.0 25.0 75.0 TEMPERATURE (C) SUPPLY VOLTAGE (V) NORMALIZED TSU VS. SUPPLY VOLTAGE (TA = 25°C) 1.2 NORMALIZED TSU VS. TEMPERATURE (VCC = 5.0V) 1.2 NORMALIZED TSU NORMALIZED TSU 1.1 1.0 0.9 1.1 1.0 0.9 0.8 4.5 4.8 5.0 SUPPLY VOLTAGE (V) 5.3 5.5 0.8 -40.0 0.0 25.0 75.
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ATF1502AS Dedicated Pinouts 44-lead TQFP 44-lead J-lead INPUT/OE2/GCLK2 40 2 INPUT/GCLR 39 1 INPUT/OE1 38 44 INPUT/GCLK1 37 43 I/O / GCLK3 35 41 I/O / PD (1,2) 5, 19 11, 25 I/O / TDI (JTAG) 1 7 I/O / TMS (JTAG) 7 13 I/O / TCK (JTAG) 26 32 I/O / TDO (JTAG) 32 38 GND 4, 16, 24, 36 10, 22, 30, 42 VCC 9, 17, 29, 41 3, 15, 23, 35 # of Signal Pins 36 36 # User I/O Pins 32 32 Dedicated Pin OE (1, 2) Global OE pins GCLR Global Clear pin GCLK (1, 2, 3) Global Clock p
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ATF1502AS(L) ATF1502AS I/O Pinouts MC PLC 44-lead PLCC 44-lead TQFP 1 A 4 42 2 A 5 43 3 A/PD1 6 44 4/TDI A 7 1 5 A 8 2 6 A 9 3 7 A 11 5 8 A 12 6 9/TMS A 13 7 10 A 14 8 11 A 16 10 12 A 17 11 13 A 18 12 14 A 19 13 15 A 20 14 16 A 21 15 17 B 41 35 18 B 40 34 19 B 39 33 20/TDO B 38 32 21 B 37 31 22 B 36 30 23 B 34 28 24 B 33 27 25/TCK B 32 26 26 B 31 25 27 B 29 23 28 B 28 22 29 B 27 21 30 B
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Ordering Information tPD (ns) tCO1 (ns) fMAX (MHz) 7.5 4.5 166.
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ATF1502AS(L) Packaging Information 44A – TQFP PIN 1 B PIN 1 IDENTIFIER E1 e E D1 D C 0˚~7˚ A1 A2 A L COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. SYMBOL MIN NOM MAX A – – 1.20 A1 0.05 – 0.
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44J – PLCC 1.14(0.045) X 45˚ PIN NO. 1 1.14(0.045) X 45˚ 0.318(0.0125) 0.191(0.0075) IDENTIFIER E1 D2/E2 B1 E B e A2 D1 A1 D A 0.51(0.020)MAX 45˚ MAX (3X) COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-018, Variation AC. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side.
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