User Manual

ATAR862-3

4556B–4BMCU–02/03

Duty Cycle Generator The duty cycle generator generates duty cycles of 25%, 33% or 50%. The frequency at

the duty cycle generator output depends on the duty cycle and the Timer 2 prescaler

setting. The DCG-stage can also be used as additional programmable prescaler for

Timer 2.

Figure 50. DCG Output Signals

T2MS1 Timer 2 Mode Select bit 1

T2MS0 Timer 2 Mode Select bit 0

Mode T2MS1 T2MS0 Clock Output (POUT) Timer 2 Modes

1 1 1 4-bit counter overflow (OVF1) 12-bit compare counter; the

DCG has to be bypassed in

this mode

2 1 0 4-bit compare output (CM1) 8-bit compare counter with 4-

bit programmable prescaler

and duty cycle generator

3 0 1 4-bit compare output (CM1) 8-bit compare counter clocked

by SYSCL or the external clock

input T2I, 4-bit prescaler run,

the counter 2/1 starts after

writing mode 3

4 0 0 4-bit compare output (CM1) 8-bit compare counter clocked

by SYSCL or the external clock

input T2I, 4-bit prescaler stop

and resets

DCGIN

DCGO0

DCGO1

DCGO2

DCGO3