User Manual

43
ATAR862-3
4556B–4BMCU–02/03
Timer 1 Control Register 2
(T1C2)
Address: "7"hex - Subaddress: "9"hex
* Bit 3 -> MSB, Bit 0 -> LSB
Watchdog Control Register
(WDC)
Address: "7"hex - Subaddress: "A"hex
* Bit 3 -> MSB, Bit 0 -> LSB
Both these bits control the time interval for the watchdog reset.
Bit 3 * Bit 2 Bit 1 Bit 0
– T1BP T1CS T1IM Reset value: x111b
T1BP Timer 1 SUBCL ByPassed
T1BP = 1, TIOUT = T1MUX
T1BP = 0, T1OUT = SUBCL
T1CS Timer 1 input Clock Select
T1CS = 1, CL1 = SUBCL (see Figure 27)
T1CS = 0, CL1 = SYSCL (see Figure 27)
T1IM Timer 1 Interrupt Mask
T1IM = 1, disables Timer 1 interrupt
T1IM = 0, enables Timer 1 interrupt
Bit 3 * Bit 2 Bit 1 Bit 0
WDL WDR WDT1 WDT0 Reset value: 1111b
WDL WatchDog Lock mode
WDL = 1, the watchdog can be enabled and disabled by using the WDR-bit
WDL = 0, the watchdog is enabled and locked. In this mode the WDR-bit has no
effect. After the WDL-bit is cleared, the watchdog is active until a
system reset or power-on reset occurs.
WDR WatchDog Run and stop mode
WDR = 1, the watchdog is stopped/disabled
WDR = 0, the watchdog is active/enabled
WDT1 WatchDog Time 1
WDT0 WatchDog Time 0
WDT1 WDT0 Divider
Delay Time to Reset with
SUBCL = 32 kHz
Delay Time to Reset with
SYSCL = 2/1 MHz
0 0 512 15.625 ms 0.256 ms/0.512 ms
0 1 2048 62.5 ms 1.024 ms/2.048 ms
1 0 16384 0.5 s 8.2 ms/16.4 ms
1 1 131072 4 s 65.5 ms/131 ms