User guide

14
4953C–AUTO–09/07
ATA6837 [Preliminary]
10. Application Circuit
Figure 10-1. Application Circuit
9. Noise and Surge Immunity
Parameters Test Conditions Value
Conducted interferences ISO 7637-1 Level 4
(1)
Interference suppression VDE 0879 Part 2 Level 5
ESD (Human Body Model) ESD S 5.1 4 kV
CDM (Charge Device Model) ESD STM5.3. 500V
Note: 1. Test pulse 5: V
vbmax
= 40V
S
I
H
S
2
L
S
2
H
S
1
L
S
1
Control
logic
CLK
DO
INH
CS
DI
Input register
Ouput register
Serial interface
H
S
3
L
S
3
H
S
2
L
S
2
H
S
1
L
S
1
S
R
R
H
S
3
L
S
3
O
L
D
H
S
5
L
S
5
H
S
4
L
S
4
H
S
6
L
S
6
P
S
F
H
S
6
L
S
6
H
S
4
T
P
L
S
4
H
S
5
L
S
5
I
N
H
S
C
D
Power on
reset
Charge
pump
UV
protection
Thermal
protection
VS
VCC
GND
GND
GND
GND
S
C
T
GND
GND
GND
GND
Fault
Detect
Fault
Detect
Fault
Detect
Fault
Detect
Fault
Detect
Fault
Detect
Fault
Detect
Fault
Detect
Fault
Detect
Fault
Detect
Fault
Detect
Fault
Detect
OUT1 OUT3OUT2 OUT4 OUT5 OUT6
M M M M M
Vbatt
24V
+
VS
BYT41D
VCC
5V
+
VCC
U5021M
Watchdog
Microcontroller
Enable
VCC
Trigger
Reset
VCC