13
4953C–AUTO–09/07
ATA6837 [Preliminary]
Figure 8-1. Serial Interface Timing Diagram with Chart Numbers
1
DO
CS
CLK
CS
DO
CLK
Output DO: High level = 0.8 × V
CC
, low level = 0.2 × V
CC
Inputs DI, CLK, CS: High level = 0.7 × V
CC
, low level = 0.2 × V
CC
DI
11
5
6 8
10 12
3
9
2
4
7
