User guide

12
4953C–AUTO–09/07
ATA6837 [Preliminary]
8. Serial Interface: Timing
Parameters Test Conditions Timing Chart No. Symbol Min. Typ. Max. Unit
DO enable after CS falling edge C
DO
= 100 pF 1 t
ENDO
200 ns
DO disable after CS rising edge C
DO
= 100 pF 2 t
DISDO
200 ns
DO fall time C
DO
= 100 pF - t
DOf
100 ns
DO rise time C
DO
= 100 pF - t
DOr
100 ns
DO valid time C
DO
= 100 pF 10 t
DOVal
200 ns
CS setup time 4t
CSSethl
225 ns
CS setup time 8t
CSSetlh
225 ns
CS high time Input register bit 14 (SCT) = high 9 t
CSh
17 ms
CS high time Input register bit 14 (SCT) = low 9 t
CSh
2.1 ms
CLK high time 5t
CLKh
225 ns
CLK low time 6t
CLKl
225 ns
CLK period time - t
CLKp
500 ns
CLK setup time 7 t
CLKSethl
225 ns
CLK setup time 3 t
CLKSetlh
225 ns
DI setup time 11 t
DIset
40 ns
DI hold time 12 t
DIHold
40 ns