Manual
3
9122B–AUTO–10/08
ATA6833/ATA6834 [Preliminary]
2. Pin Configuration
Figure 2-1. Pinning QFN48
Note: YWW Date code (Y = Year - above 2000, WW = week number)
ATA683x Product name
ZZZZZ Wafer lot number
AL Assembly sub-lot number
RWD
WDD
EN1
NC
NC
GND
NC
CC
WD
/RESET
VMODE
VINT
Atmel YWW
ATA6833/ATA6834
ZZZZZ-AL
CPLO1
CPHI1
CPLO2
CPHI2
CPOUT
S1
H1
S2
H2
S3
H3
DG3
NC
PBAT
VG
L1
L2
L3
PGND
VBAT
EN2
VBATSW
NC
VCC
TXD
IH3
IL2
IH2
RXD
DG1
DG2
IH1
IL1
IL3
NC
LIN
48 47 46 45 44 43 42 41 40 39 38 37
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
Table 2-1. Pin Description
Pin Symbol I/O Function
1 VMODE I Selector for V
CC
and interface logic voltage level
2 VINT I/O Blocking capacitor
3 RWD I Resistor defining the watchdog interval
4 CC I/O RC combination to adjust cross conduction time
5 /RESET O Reset signal for microcontroller
6 WD I Watchdog trigger signal
7 WDD I Enable and disable the watchdog
8 EN1 I Microcontroller output to switch system in Sleep Mode
9 N.C. Connect to GND
10 N.C. Connect to GND
11 GND I Ground
12 NC Connect to GND
13 LIN I/O LIN-bus terminal
14 NC Connect to GND
15 TXD I Transmit signal to LIN bus from microcontroller
16 IL3 I Control Input for output L3
17 IH3 I Control Input for output H3