Manual

11
4951A–AUTO–08/06
ATA6832
4.14
Open load detection
current ratio
IOL
outLX
/
IOL
outHX
1.2 3
4.15
High-side output switch
on delay
(1),(2)
V
VS
= 13V
R
Load
=30Ω
t
don
20 µs A
4.16
Low-side output switch
on delay
(1),(2)
V
VS
= 13V
R
Load
=30Ω
t
don
20 µs A
4.17
High-side output switch
off delay
(1),(2)
V
VS
=13V
R
Load
= 30Ω
t
doff
20 µs A
4.18
Low-side output switch
off delay
(1),(2)
V
VS
=13V
R
Load
= 30Ω
t
doff
3 µsA
4.19
Dead time between
corresponding
high-side and low-side
switches
V
VS
=13V
R
Load
= 30Ω
t
don
– t
doff
1 µsA
4.20
∆t
dPWM
low-side switch
(3)
V
VS
= 13V
R
Load
= 30Ω
∆t
dPWM
=
t
don
– t
doff
20 µs A
4.21
∆t
dPWM
high-side switch
(3)
V
VS
= 13V
R
Load
= 30Ω
∆t
dPWM
=
t
don
– t
doff
37 µsA
5 Logic Inputs DI, CLK, CS, PWM
5.1
Input voltage low-level
threshold
3, 4, 5,
6
V
IL
0.3 ×
V
VCC
VA
5.2
Input voltage high-level
threshold
3, 4, 5,
6
V
IH
0.7 ×
V
VCC
VA
5.3
Hysteresis of input
voltage
3, 4, 5,
6
∆V
I
50 700 mV A
5.4
Pull-down current
pins DI, CLK, PWM
V
DI
, V
CLK,
V
PWM
= V
CC
4, 5, 6 I
PD
570 µAA
5.5
Pull-up current
pin CS
V
CS
= 0V 3 I
PU
–70 –5 µA A
6 Serial Interface – Logic Output DO
6.1 Output-voltage low level I
DOL
= 2 mA 7 V
DOL
0.4 V A
6.2
Output-voltage high
level
I
DOL
= –2 mA 7 V
DOH
V
VCC
–
0.7V
VA
6.3
Leakage current
(tri-state)
V
CS
= V
CC
0V < V
DO
< V
VCC
7I
DO
–15 +15 µA A
7 Inhibit Input – Timing
7.1
Delay time from
standby to normal
operation
t
dINH
100 µs A
8. Electrical Characteristics (Continued)
7.5V < V
S
< 40V; 4.75V < V
CC
< 5.25V; INH = High; –40°C ≤ T
j
≤ 200°C; T
a
≤ 150°C; unless otherwise specified, all values refer to
GND pins.
No. Parameters Test Conditions
Pin
Symbol Min. Typ. Max. Unit Type*
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes: 1. Delay time between rising edge of input signal at pin CS after data transmission and switch on/off output stages to 90% of
final level. Device not in standby for t > 1 ms.
2. Delay time between rising/falling edge of input signal at pin PWM and switch on/off output stages to 90% of final level.
3. Difference between switch-on and switch-off delay time of input signal at pin PWM to output stages in PWM mode.