Manual
10
4951A–AUTO–08/06
ATA6832
3.5 Thermal shutdown on T
j switch on
185 210 235 °C B
3.6
Thermal shutdown
hysteresis
∆T
j switch off
15 K B
3.7
Ratio thermal shutdown
off/thermal prewarning
set
T
j switch off/
T
jPW set
1.05 1.2 B
3.8
Ratio thermal shutdown
on/thermal prewarning
reset
T
j switch on/
T
jPW reset
1.05 1.2 B
4 Output Specification (OUT1 to OUT3)
4.1
On resistance
I
Out 1-3
= –0.9 A
2, 12,
15
R
DSon1-3H
1.5 Ω A
4.2 I
Out 1-3
= –0.9 A
2, 12,
15
R
DSon1-3L
1.5 Ω A
4.3
High-side output
leakage current
V
Out 1-3 H
= 0V
,
output stages off
2, 12,
15
I
Out1-3H
–60 µA A
4.4
Low-side output
leakage current
V
Out 1-3 L
= V
VS,
output stages off
2, 12,
15
I
Out1-3L
300 µA A
4.5
High-side switch
reverse diode forward
voltage
I
Out
= 1.5A
2, 12,
15
V
Out1-3
– V
VS
2VA
4.6
Low-side switch reverse
diode forward voltage
I
Out 1-3 L
= –1.5A
2, 12,
15
V
Out1-3L
2VA
4.7
High-side overcurrent
limitation and shutdown
threshold
7.5V < V
VS
< 20V
2, 12,
15
I
Out1-3
1.0 1.3 1.7 A A
4.8
Low-side overcurrent
limitation and shutdown
threshold
7.5V < V
VS
< 20V
2, 12,
15
I
Out1-3
–1.7 –1.3 –1.0 A A
4.9
High-side overcurrent
limitation and shutdown
threshold
20V < V
VS
< 40V
2, 12,
15
I
Out1-3
1.0 1.3 2.0 A A
4.10
Low-side overcurrent
limitation and shutdown
threshold
20V < V
VS
< 40V
2, 12,
15
I
Out1-3
–2.0 –1.3 –1.0 A A
4.11
Overcurrent shutdown
delay time
t
dSd
10 40 µs A
4.12
High-side open load
detection current
Input register bit 13
(OLD) = low, output off
2, 12,
15
I
Out1-3H
–2.5 –0.2 mA A
4.13
Low-side open load
detection current
Input register bit 13
(OLD) = low, output off
2, 12,
15
I
Out1-3L
0.2 2.5 mA A
8. Electrical Characteristics (Continued)
7.5V < V
S
< 40V; 4.75V < V
CC
< 5.25V; INH = High; –40°C ≤ T
j
≤ 200°C; T
a
≤ 150°C; unless otherwise specified, all values refer to
GND pins.
No. Parameters Test Conditions
Pin
Symbol Min. Typ. Max. Unit Type*
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes: 1. Delay time between rising edge of input signal at pin CS after data transmission and switch on/off output stages to 90% of
final level. Device not in standby for t > 1 ms.
2. Delay time between rising/falling edge of input signal at pin PWM and switch on/off output stages to 90% of final level.
3. Difference between switch-on and switch-off delay time of input signal at pin PWM to output stages in PWM mode.