Manual

2
ATA6830
4575B–BCD–01/03
Figure 1. Block Diagram
Pin Configuration
Figure 2. Pinning HP-VFQFP-N28
SRB
SM1B
VBAT1B
SM2B
VBAT2B
SRA
SM1A
VBAT1A
SM2A
VBAT2A
Driver Logic
Cruising Service Control
Driver Logic
UART
Command Interpreter
Test Logic
BUS
Voltage
Regulator
VSS
VDD
Biasing
RSET
Oscillator
COS
Temperature Monitor
Supply Monitor
AGND
ATA6830
MLP 7x7mm
0.8mm pitch
28 lead
8 9 10 11 12 13 14
28 27 26 25 24 23 22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
ATA6830
VBAT1B
n.c.
SM1B
SRB
SM2B
n.c.
VBAT2B
n.c. COS RSET AGND VSS VDD BUS
n.c.
SCI1
SCO1
SCI2
SCO2
TA
TTEMP
VBAT1A
n.c.
SM1A
SRA
SM2A
n.c.
VBAT2A