User guide

61
ATA5811/ATA5812 [Preliminary]
4689B–RKE–04/04
Interrupts Via pin IRQ, the transceiver signals different operating conditions to a connected micro-
controller. If a specific operating condition occurs, pin IRQ is set to high level.
If an interrupt occurs it is recommended to delete the interrupt be immediately deleted
by reading the status register, thus the next possible interrupt doesn’t get lost. If the
Interrupt pin doesn’t switch to low level by reading the status register the interrupt was
triggered by the RX/TX data buffer. In this case read or write the RX/TX data buffer
according to Table 42.
Table 41. TX Modulation Schemes
Mode ASK/_NFSK P_Mode T_Mode
Bit in TX/RX
Data Buffer
Level on Pin
SDI_TMDI RF
OUT
TX
0
001Xf
FSK_L
→ f
FSK_H
000Xf
FSK_H
→ f
FSK_L
101X f
FSK_H
100X f
FSK_L
X1X1 f
FSK_H
X1X0 f
FSK_L
1
001Xf
ASK
off → f
ASK
on
000Xf
ASK
on → f
ASK
off
101X f
ASK
on
100X f
ASK
off
X1X1 f
ASK
on
X1X0 f
ASK
off
Table 42. Interrupt Handling
Operating Conditions Which Sets Pin
IRQ to High Level Operations Which Sets Pin IRQ to Low Level
Events in Status Register
State transition of status bit STn
(0 → 1; 1 → 0)
Read status register or
Command Delete IRQ
Appearance of status bit Power_On
(0 → 1)
Appearance of status bit P_On_Aux
(0 → 1)
Events During TX Operation (T_MODE = 0)
4, 8 or 12 Bytes are in the TX data buffer or
the TX data buffer is empty (depends on IR0
and IR1 in control register 1).
Write TX data buffer or
Write control register 1 or
Write control register 4 or
Write control register 5 or
Write control register 6 or
Command delete IRQ
Events During RX Operation (T_MODE = 0)
4, 8 or 12 received bytes are in the RX data
buffer or a receiving error is occurred
(depends on IR0 and IR1 in control
register 1).
Read RX data buffer or
Write control register 1 or
Write control register 4 or
Write control register 5 or
Write control register 6 or
Command delete IRQ
Successful Bit-check (P_MODE = 0)