User guide

5
ATA5811/ATA5812 [Preliminary]
4689B–RKE–04/04
Figure 3. Block Diagram
R_PWR
RF_OUT
RX_TX2
RF_IN
AVCC
GND
Signal
Processing
(Mixer, IF -
Filter, IF -
Amp.,
Demodulator,
Data Filter
Data Slicer)
RF transceiver Digital Control Logic
DVCC
PA_Enable (ASK)
RX/TX
Frontend Enable
Demod_Out
XTAL1
XTAL2
CLK
N_RESET
CS
SCK
SDI_TMDI
SDO_TMDO
VS2
VS1
VAUX
VSOUT
T1
PWR_ON
CDEM
433_N868
RX_TX1
PWR_H
RSSI
IRQ
DEM_OUT
Microcontroller
Interface
VSINT
PA
Fract.-N-
Frequency
Synthesizer
LNA
SPI
XTO
FREF
TX/RX - Data Buffer
Control Register
Status Register
Polling Circuit
Bit-Check Logic
RX_ACTIVE
TEST1
TEST2
T2
T3
T4
T5
FREQ 9
TX_DATA (FSK)
Power
Supply
Switches
Regulators
Wakeup
Reset
Reset
TX