User guide

33
ATA5811/ATA5812 [Preliminary]
4689B–RKE–04/04
After the transceiver is turned on via pin PWR_ON = High, T1 = Low, T2 = Low,
T3 = Low, T4 = Low or T5 = Low or the voltage at pin VAUX V
VAUX
> 3.5 V (typically) the
control registers are in the default state.
Figure 27. Register Structure
MSB
LSB
Status Register (ADR 8)
Control Register 1 (ADR 0)
Control Register 4 (ADR 3)
ST5 ST4 ST3 ST2 ST1
BitChk1 BitChk0
ASK/
NFSK
Sleep4 Sleep3 Sleep2 Sleep1
Sleep0
XSleep
Lim_min5
Lim_max5
IR1 IR0
TX/RX Data Buffer:
16 × 8 Bit
OPM 1
-
T_MODE
Control Register 5 (ADR 4)
Control Register 6 (ADR 5)
Power_
On
Control Register 2 (ADR 1)
FR4 FR3 FR2 FR1 FR0
Control Register 3 (ADR 2)
----FR8
Low_
Batt
P_On_
Aux
FS
AVCC_
EN
FR5FR6
FR7
VSOUT_
En
CLK_ON
XLim
Baud1 Baud0
OPM 0
P_MODE
Lim_min0Lim_min1Lim_min2Lim_min3Lim_min4
Lim_max0
Lim_max1
Lim_max2Lim_max3Lim_max4