User guide

ATA5811/ATA5812 [Preliminary]

4689B–RKE–04/04

If V

VSOUT

drops below V

Thres_1

(typically 2.3 V), N_RESET is set to low. If bit VSOUT_EN

in control register

3 is 1, a DVCC_RESET is also generated. If V

VSOUT

was prior dis-

abled by the connected microcontroller by setting bit VSOUT_EN = 0, no

DVCC_RESET is generated.

Note: If VSOUT < V

Thres_1

(typically 2.3 V) the output of the pin CLK is low, the

Microcontroller_Interface is disabled and the transceiver is not programmable via the

4-wire serial interface.

Figure 23. Reset Timing

VSOUT

DVCC

(AVCC)

DVCC_RESET

Thres_1

= 2.3 V (typ)

N_RESET

Low_Batt

(Status Register)

VSOUT_EN

(Control Register 3)

1.5 V (typically)

CLK

VSOUT

> 2.3 V and the XTO is running

VSOUT

> 2.38 V and the XTO is running

Thres_2

= 2.38 V (typ)