Manual
Table Of Contents
- Features
- Pin Configurations
- Description
- Architectural Overview- General Purpose Register File
- ALU – Arithmetic Logic Unit
- In-System Programmable Flash Program Memory
- SRAM Data Memory
- Program and Data Addressing Modes- Register Direct, Single Register Rd
- Register Direct, Two Registers Rd and Rr
- I/O Direct
- Data Direct
- Data Indirect with Displacement
- Data Indirect
- Data Indirect with Pre- decrement
- Data Indirect with Post- increment
- Constant Addressing Using the LPM Instruction
- Indirect Program Addressing, IJMP and ICALL
- Relative Program Addressing, RJMP and RCALL
 
- EEPROM Data Memory
- Memory Access Times and Instruction Execution Timing
- I/O Memory
- Reset and Interrupt Handling- Reset Sources
- Power-on Reset
- External Reset
- Brown-out Detection
- Watchdog Reset
- MCU Status Register – MCUSR
- Interrupt Handling
- General Interrupt Mask Register – GIMSK
- General Interrupt Flag Register – GIFR
- Timer/Counter Interrupt Mask Register – TIMSK
- Timer/Counter Interrupt Flag Register – TIFR
- External Interrupts
- Interrupt Response Time
- MCU Control Register – MCUCR
 
- Sleep Modes
 
- Timer/Counters
- 16-bit Timer/Counter1
- Watchdog Timer
- EEPROM Read/Write Access
- Serial Peripheral Interface – SPI
- UART
- Analog Comparator
- Analog-to-Digital Converter
- I/O Ports
- Memory Programming
- Electrical Characteristics
- External Clock Drive Waveforms
- Typical Characteristics
- Register Summary
- Instruction Set Summary
- Ordering Information
- Packaging Information
- Errata for AT90S/LS4433 Rev. Rev. C/D/E/F
- Data Sheet ChangeLog for AT90S/LS4433
- Table of Contents

99
AT90S/LS4433
1042G–AVR–09/02
Notes: 1. “Max” means the highest value where the pin is guaranteed to be read as low (logical “0”).
2. “Min” means the lowest value where the pin is guaranteed to be read as high (logical “1”).
3. Although each I/O port can sink more than the test conditions (20 mA at V
CC
= 5.0V, 10 mA at V
CC
= 3.0V) under steady-
state conditions (non-transient), the following must be observed:
1] The sum of all I
OL
, for all ports, should not exceed 300 mA.
2] The sum of all I
OL
, for ports C0 - C5, should not exceed 100 mA.
3] The sum of all I
OL
, for ports B0 - B5, D0 - D7 and XTAL2, should not exceed 200 mA.
If I
OL
exceeds the test condition, V
OL
may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test condition.
4. Although each I/O port can source more than the test conditions (3 mA at V
CC
=5.0V,1.5mAatV
CC
= 3.0V) under steady-
state conditions (non-transient), the following must be observed:
1] The sum of all I
OH
, for all ports, should not exceed 300 mA.
2] The sum of all I
OH
, for ports C0 - C5, should not exceed 100 mA.
3] The sum of all I
OH
, for ports B0 - B5, D0 - D7 and XTAL2, should not exceed 200 mA.
If I
OH
exceeds the test condition, V
OH
may exceed the related specification. Pins are not guaranteed to source current
greater than the listed test condition.
5. Minimum V
CC
for Power-down is 2.0V.
V
ACIO
Analog Comparator Input
Offset Voltage
V
CC
=5.0V
V
in
=V
CC
/2
40.0 mV
I
ACLK
Analog Comparator Input
Leakage A
V
CC
=5.0V
V
in
=V
CC
/2
-50.0 50.0 nA
t
ACPD
Analog Comparator
Propagation Delay
V
CC
=2.7V
V
CC
=4.0V
750.0
500.0
ns
DC Characteristics (Continued)
T
A
=-40°Cto85°C, V
CC
= 2.7V to 6.0V (unless otherwise noted)
Symbol Parameter Condition Min Typ Max Units










