Manual
Table Of Contents
- Features
- Pin Configurations
- Description
- Architectural Overview
- General Purpose Register File
- ALU – Arithmetic Logic Unit
- In-System Programmable Flash Program Memory
- SRAM Data Memory
- Program and Data Addressing Modes
- Register Direct, Single Register Rd
- Register Direct, Two Registers Rd and Rr
- I/O Direct
- Data Direct
- Data Indirect with Displacement
- Data Indirect
- Data Indirect with Pre- decrement
- Data Indirect with Post- increment
- Constant Addressing Using the LPM Instruction
- Indirect Program Addressing, IJMP and ICALL
- Relative Program Addressing, RJMP and RCALL
- EEPROM Data Memory
- Memory Access Times and Instruction Execution Timing
- I/O Memory
- Reset and Interrupt Handling
- Reset Sources
- Power-on Reset
- External Reset
- Brown-out Detection
- Watchdog Reset
- MCU Status Register – MCUSR
- Interrupt Handling
- General Interrupt Mask Register – GIMSK
- General Interrupt Flag Register – GIFR
- Timer/Counter Interrupt Mask Register – TIMSK
- Timer/Counter Interrupt Flag Register – TIFR
- External Interrupts
- Interrupt Response Time
- MCU Control Register – MCUCR
- Sleep Modes
- Timer/Counters
- 16-bit Timer/Counter1
- Watchdog Timer
- EEPROM Read/Write Access
- Serial Peripheral Interface – SPI
- UART
- Analog Comparator
- Analog-to-Digital Converter
- I/O Ports
- Memory Programming
- Electrical Characteristics
- External Clock Drive Waveforms
- Typical Characteristics
- Register Summary
- Instruction Set Summary
- Ordering Information
- Packaging Information
- Errata for AT90S/LS4433 Rev. Rev. C/D/E/F
- Data Sheet ChangeLog for AT90S/LS4433
- Table of Contents
97
AT90S/LS4433
1042G–AVR–09/02
Serial Programming
Characteristics
Figure 68. Serial Programming Timing
Table 36. Serial Programming Characteristics, T
A
=-40°Cto85°C, V
CC
=2.7-6.0V
(unless otherwise noted)
Symbol Parameter Min Typ Max Units
1/t
CLCL
Oscillator Frequency (V
CC
= 2.7 - 6.0V) 0 4 MHz
t
CLCL
Oscillator Period (V
CC
=2.7-6.0V) 250 ns
1/t
CLCL
Oscillator Frequency (V
CC
= 4.0 - 6.0V) 0 8 MHz
t
CLCL
Oscillator Period (V
CC
=4.0-6.0V) 125 ns
t
SHSL
SCK Pulse Width High 2 t
CLCL
ns
t
SLSH
SCK Pulse Width Low 2 t
CLCL
ns
t
OVSH
MOSI Setup to SCK High t
CLCL
ns
t
SHOX
MOSI Hold after SCK High 2 t
CLCL
ns
t
SLIV
SCK Low to MISO Valid 10 16 32 ns
Table 37. Minimum Wait Delay after the Chip Erase Instruction
Symbol 3.2V 3.6V 4.0V 5.0V
t
WD_ERASE
18 ms 14 ms 12 ms 8 ms
Table 38. Minimum Wait Delay after Writing a Flash or EEPROM Location
Symbol 3.2V 3.6V 4.0V 5.0V
t
WD_PROG
9ms 7ms 6ms 4ms
MOSI
MISO
SCK
t
OVSH
t
SHSL
t
SLSH
t
SHOX
t
SLIV