Manual
Table Of Contents
- Features
- Pin Configurations
- Description
- Architectural Overview
- General Purpose Register File
- ALU – Arithmetic Logic Unit
- In-System Programmable Flash Program Memory
- SRAM Data Memory
- Program and Data Addressing Modes
- Register Direct, Single Register Rd
- Register Direct, Two Registers Rd and Rr
- I/O Direct
- Data Direct
- Data Indirect with Displacement
- Data Indirect
- Data Indirect with Pre- decrement
- Data Indirect with Post- increment
- Constant Addressing Using the LPM Instruction
- Indirect Program Addressing, IJMP and ICALL
- Relative Program Addressing, RJMP and RCALL
- EEPROM Data Memory
- Memory Access Times and Instruction Execution Timing
- I/O Memory
- Reset and Interrupt Handling
- Reset Sources
- Power-on Reset
- External Reset
- Brown-out Detection
- Watchdog Reset
- MCU Status Register – MCUSR
- Interrupt Handling
- General Interrupt Mask Register – GIMSK
- General Interrupt Flag Register – GIFR
- Timer/Counter Interrupt Mask Register – TIMSK
- Timer/Counter Interrupt Flag Register – TIFR
- External Interrupts
- Interrupt Response Time
- MCU Control Register – MCUCR
- Sleep Modes
- Timer/Counters
- 16-bit Timer/Counter1
- Watchdog Timer
- EEPROM Read/Write Access
- Serial Peripheral Interface – SPI
- UART
- Analog Comparator
- Analog-to-Digital Converter
- I/O Ports
- Memory Programming
- Electrical Characteristics
- External Clock Drive Waveforms
- Typical Characteristics
- Register Summary
- Instruction Set Summary
- Ordering Information
- Packaging Information
- Errata for AT90S/LS4433 Rev. Rev. C/D/E/F
- Data Sheet ChangeLog for AT90S/LS4433
- Table of Contents
94
AT90S/LS4433
1042G–AVR–09/02
ing the third byte of the Programming Enable instruction. Whether or not the
echo is correct, all four bytes of the instruction must be transmitted. If the $53 did
not echo back, give SCK a positive pulse and issue a new Programming Enable
instruction. If the $53 is not seen within 32 attempts, there is no functional device
connected.
4. If a Chip Erase is performed (must be done to erase the Flash), wait t
WD_ERASE
after the instruction, give RESET a positive pulse, and start over from step 2.
See Table 37 on page 97 for t
WD_ERASE
value.
5. The Flash or EEPROM array is programmed one byte at a time by supplying the
address and data together with the appropriate Write instruction. An EEPROM
memory location is first automatically erased before new data is written. Use
data polling to detect when the next byte in the Flash or EEPROM can be writ-
ten. If polling is not used, wait t
WD_PROG
before transmitting the next instruction. In
an erased device, no $FFs in the data file(s) need to be programmed. See Table
38 on page 97 for t
WD_PROG
value.
6. Any memory location can be verified by using the Read instruction, which returns
the content at the selected address at serial output MISO/PB4.
7. At the end of the programming session, RESET
can be set high to commence
normal operation.
8. Power-off sequence (if needed):
Set XTAL1 to “0” (if a crystal is not used).
Set RESET
to “1”.
Tu r n V
CC
power off.
Data Polling EEPROM When a byte is being programmed into the EEPROM, reading the address location
being programmed will give the value P1 until the auto-erase is finished, and then the
value P2. See Table 34 for P1 and P2 values.
At the time the device is ready for a new EEPROM byte, the programmed value will read
correctly. This is used to determine when the next byte can be written. This will not work
for the values P1 and P2, so when programming these values, the user will have to wait
for at least the prescribed time t
WD_PROG
before programming the next byte. See Table
38 for t
WD_PROG
value. As a chip-erased device contains $FF in all locations, program-
ming of addresses that are meant to contain $FF can be skipped. This does not apply if
the EEPROM is reprogrammed without first Chip Erasing the device.
Table 34. Read Back Value during EEPROM Polling
Part P1 P2
AT90S/LS4433 $00 $FF