Manual
Table Of Contents
- Features
- Pin Configurations
- Description
- Architectural Overview
- General Purpose Register File
- ALU – Arithmetic Logic Unit
- In-System Programmable Flash Program Memory
- SRAM Data Memory
- Program and Data Addressing Modes
- Register Direct, Single Register Rd
- Register Direct, Two Registers Rd and Rr
- I/O Direct
- Data Direct
- Data Indirect with Displacement
- Data Indirect
- Data Indirect with Pre- decrement
- Data Indirect with Post- increment
- Constant Addressing Using the LPM Instruction
- Indirect Program Addressing, IJMP and ICALL
- Relative Program Addressing, RJMP and RCALL
- EEPROM Data Memory
- Memory Access Times and Instruction Execution Timing
- I/O Memory
- Reset and Interrupt Handling
- Reset Sources
- Power-on Reset
- External Reset
- Brown-out Detection
- Watchdog Reset
- MCU Status Register – MCUSR
- Interrupt Handling
- General Interrupt Mask Register – GIMSK
- General Interrupt Flag Register – GIFR
- Timer/Counter Interrupt Mask Register – TIMSK
- Timer/Counter Interrupt Flag Register – TIFR
- External Interrupts
- Interrupt Response Time
- MCU Control Register – MCUCR
- Sleep Modes
- Timer/Counters
- 16-bit Timer/Counter1
- Watchdog Timer
- EEPROM Read/Write Access
- Serial Peripheral Interface – SPI
- UART
- Analog Comparator
- Analog-to-Digital Converter
- I/O Ports
- Memory Programming
- Electrical Characteristics
- External Clock Drive Waveforms
- Typical Characteristics
- Register Summary
- Instruction Set Summary
- Ordering Information
- Packaging Information
- Errata for AT90S/LS4433 Rev. Rev. C/D/E/F
- Data Sheet ChangeLog for AT90S/LS4433
- Table of Contents
91
AT90S/LS4433
1042G–AVR–09/02
Programming the Fuse Bits The algorithm for programming the Fuse bits is as follows (refer to “Programming the
Flash” for details on command and data loading):
A: Load Command “0100 0000”.
B: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.
Bit 5 = SPIEN Fuse bit
Bit 4 = BODLEVEL Fuse bit
Bit 3 = BODEN Fuse bit
Bit 2 = CKSEL2 Fuse bit
Bit 1 = CKSEL1 Fuse bit
Bit 0 = CKSEL0 Fuse bit
Bits7-6=“1”. These bits are reserved and should be left unprogrammed (“1”).
1. Give WR
at
WLWH_PFB
wide negative pulse to execute the programming, t
WLWH_PFB
is found in Table 33. Programming the Fuse bits does not generate any activity
on the RDY/BSY
pin.
Programming the Lock Bits The algorithm for programming the Lock bits is as follows (refer to “Programming the
Flash” for details on command and data loading):
A: Load Command “0010 0000”.
B: Load Data Low Byte. Bit n = “0” programs the Lock bit.
Bit 2 = Lock bit 2
Bit 1 = Lock bit 1
Bits7-3,0=“1”. These bits are reserved and should be left unprogrammed (“1”).
C: Write Data Low Byte.
The Lock bits can only be cleared by executing Chip Erase.
Reading the Fuse and Lock
Bits
The algorithm for reading the Fuse and Lock bits is as follows (refer to “Programming
the Flash” for details on command loading):
A: Load Command “0000 0100”.
1. Set OE
to “0”, and BS to “0”. The status of the Fuse bits can now be read at
DATA (“0” means programmed).
Bit 5 = SPIEN Fuse bit
Bit 4 = BODLEVEL Fuse bit
Bit 3 = BODEN Fuse bit
Bit 2 = CKSEL2 Fuse bit
Bit 1 = CKSEL1 Fuse bit
Bit 0 = CKSEL0 Fuse bit
2. Set BS to “1”. The status of the Lock bits can now be read at DATA (“0” means
programmed).
Bit 2 = Lock Bit 2
Bit 1= Lock Bit 1
3. Set OE
to “1”.