Manual
Table Of Contents
- Features
- Pin Configurations
- Description
- Architectural Overview
- General Purpose Register File
- ALU – Arithmetic Logic Unit
- In-System Programmable Flash Program Memory
- SRAM Data Memory
- Program and Data Addressing Modes
- Register Direct, Single Register Rd
- Register Direct, Two Registers Rd and Rr
- I/O Direct
- Data Direct
- Data Indirect with Displacement
- Data Indirect
- Data Indirect with Pre- decrement
- Data Indirect with Post- increment
- Constant Addressing Using the LPM Instruction
- Indirect Program Addressing, IJMP and ICALL
- Relative Program Addressing, RJMP and RCALL
- EEPROM Data Memory
- Memory Access Times and Instruction Execution Timing
- I/O Memory
- Reset and Interrupt Handling
- Reset Sources
- Power-on Reset
- External Reset
- Brown-out Detection
- Watchdog Reset
- MCU Status Register – MCUSR
- Interrupt Handling
- General Interrupt Mask Register – GIMSK
- General Interrupt Flag Register – GIFR
- Timer/Counter Interrupt Mask Register – TIMSK
- Timer/Counter Interrupt Flag Register – TIFR
- External Interrupts
- Interrupt Response Time
- MCU Control Register – MCUCR
- Sleep Modes
- Timer/Counters
- 16-bit Timer/Counter1
- Watchdog Timer
- EEPROM Read/Write Access
- Serial Peripheral Interface – SPI
- UART
- Analog Comparator
- Analog-to-Digital Converter
- I/O Ports
- Memory Programming
- Electrical Characteristics
- External Clock Drive Waveforms
- Typical Characteristics
- Register Summary
- Instruction Set Summary
- Ordering Information
- Packaging Information
- Errata for AT90S/LS4433 Rev. Rev. C/D/E/F
- Data Sheet ChangeLog for AT90S/LS4433
- Table of Contents
88
AT90S/LS4433
1042G–AVR–09/02
Chip Erase The Chip Erase command will erase the Flash and EEPROM memories and the Lock
bits. The Lock bits are not reset until the Flash and EEPROM have been completely
erased. The Fuse bits are not changed. Chip Erase must be performed before the Flash
or EEPROM is reprogrammed.
A: Load Command “Chip Erase”
1. SetXA1,XA0to“10”. This enables command loading.
2. Set BS to “0”.
3. Set DATA to “1000 0000”. This is the command for Chip Erase.
4. Give XTAL1 a positive pulse. This loads the command.
5. Give WR
at
WLWH_CE
wide negative pulse to execute Chip Erase. See Table 33 for
t
WLWH_CE
value. Chip Erase does not generate any activity on the RDY/BSY pin.
Programming the Flash A: Load Command “Write Flash”
1. SetXA1,XA0to“10”. This enables command loading.
2. Set BS to “0”.
3. Set DATA to “0001 0000”. This is the command for Write Flash.
4. Give XTAL1 a positive pulse. This loads the command.
B: Load Address High Byte
1. SetXA1,XA0to“00”. This enables address loading.
2. Set BS to “1”. This selects High Byte.
3. Set DATA = Address High Byte ($00 - $07).
4. Give XTAL1 a positive pulse. This loads the address High Byte.
C: Load Address Low Byte
1. SetXA1,XA0to“00”. This enables address loading.
2. Set BS to “0”. This selects Low Byte.
3. Set DATA = Address Low Byte ($00 - $FF).
4. Give XTAL1 a positive pulse. This loads the address Low Byte.
D: Load Data Low Byte
1. SetXA1,XA0to“01”. This enables data loading.
2. Set DATA = Data Low Byte ($00 - $FF).
3. Give XTAL1 a positive pulse. This loads the data Low Byte.
E: Write Data Low Byte
1. Set BS to “0”. This selects low data.
2. Give WR
a negative pulse. This starts programming of the data byte. RDY/BSY
goes low.
3. Wait until RDY/BSY
goes high to program the next byte.
(See Figure 63 for signal waveforms.)
F: Load Data High Byte
1. SetXA1,XA0to“01”. This enables data loading.
2. Set DATA = Data High Byte ($00 - $FF).
3. Give XTAL1 a positive pulse. This loads the data High Byte.