Manual
Table Of Contents
- Features
- Pin Configurations
- Description
- Architectural Overview
- General Purpose Register File
- ALU – Arithmetic Logic Unit
- In-System Programmable Flash Program Memory
- SRAM Data Memory
- Program and Data Addressing Modes
- Register Direct, Single Register Rd
- Register Direct, Two Registers Rd and Rr
- I/O Direct
- Data Direct
- Data Indirect with Displacement
- Data Indirect
- Data Indirect with Pre- decrement
- Data Indirect with Post- increment
- Constant Addressing Using the LPM Instruction
- Indirect Program Addressing, IJMP and ICALL
- Relative Program Addressing, RJMP and RCALL
- EEPROM Data Memory
- Memory Access Times and Instruction Execution Timing
- I/O Memory
- Reset and Interrupt Handling
- Reset Sources
- Power-on Reset
- External Reset
- Brown-out Detection
- Watchdog Reset
- MCU Status Register – MCUSR
- Interrupt Handling
- General Interrupt Mask Register – GIMSK
- General Interrupt Flag Register – GIFR
- Timer/Counter Interrupt Mask Register – TIMSK
- Timer/Counter Interrupt Flag Register – TIFR
- External Interrupts
- Interrupt Response Time
- MCU Control Register – MCUCR
- Sleep Modes
- Timer/Counters
- 16-bit Timer/Counter1
- Watchdog Timer
- EEPROM Read/Write Access
- Serial Peripheral Interface – SPI
- UART
- Analog Comparator
- Analog-to-Digital Converter
- I/O Ports
- Memory Programming
- Electrical Characteristics
- External Clock Drive Waveforms
- Typical Characteristics
- Register Summary
- Instruction Set Summary
- Ordering Information
- Packaging Information
- Errata for AT90S/LS4433 Rev. Rev. C/D/E/F
- Data Sheet ChangeLog for AT90S/LS4433
- Table of Contents
87
AT90S/LS4433
1042G–AVR–09/02
Enter Programming Mode The following algorithm puts the device in Parallel Programming mode:
1. Apply supply voltage according to Table 29, between V
CC
and GND.
2. Set the RESET
and BS pin to “0” and wait at least 100 ns.
3. Apply 11.5 - 12.5V to RESET
. Any activity on BS within 100 ns after +12V has
been applied to RESET
will cause the device to fail entering Programming mode.
Table 30. Pin Name Mapping
Signal Name in
Programming Mode Pin Name I/O Function
RDY/BSY
PD1 O
0: Device is busy programming, 1: Device is
ready for new command
OE
PD2 I Output Enable (active low)
WR
PD3 I WritePulse(activelow)
BS PD4 I
Byte Select (“0” selects Low Byte, “1”
selects High Byte)
XA0 PD5 I XTAL Action Bit 0
XA1 PD6 I XTAL Action Bit 1
DATA PC1 - 0, PB5 - 0 I/O
Bi-directional Data Bus (output when OE
is
low)
Table 31. XA1 and XA0 Coding
XA1 XA0 Action when XTAL1 is Pulsed
0 0 Load Flash or EEPROM Address (high or low address byte determined by BS)
0 1 Load Data (high or low data byte for Flash determined by BS)
1 0 Load Command
1 1 No Action, Idle
Table 32. Command Byte Bit Coding
Command Byte Command Executed
1000 0000 Chip Erase
0100 0000 Write Fuse Bits
0010 0000 Write Lock Bits
0001 0000 Write Flash
0001 0001 Write EEPROM
0000 1000 Read Signature Bytes
0000 0100 Read Fuse and Lock Bits
0000 0010 Read Flash
0000 0011 Read EEPROM