Manual
Table Of Contents
- Features
- Pin Configurations
- Description
- Architectural Overview
- General Purpose Register File
- ALU – Arithmetic Logic Unit
- In-System Programmable Flash Program Memory
- SRAM Data Memory
- Program and Data Addressing Modes
- Register Direct, Single Register Rd
- Register Direct, Two Registers Rd and Rr
- I/O Direct
- Data Direct
- Data Indirect with Displacement
- Data Indirect
- Data Indirect with Pre- decrement
- Data Indirect with Post- increment
- Constant Addressing Using the LPM Instruction
- Indirect Program Addressing, IJMP and ICALL
- Relative Program Addressing, RJMP and RCALL
- EEPROM Data Memory
- Memory Access Times and Instruction Execution Timing
- I/O Memory
- Reset and Interrupt Handling
- Reset Sources
- Power-on Reset
- External Reset
- Brown-out Detection
- Watchdog Reset
- MCU Status Register – MCUSR
- Interrupt Handling
- General Interrupt Mask Register – GIMSK
- General Interrupt Flag Register – GIFR
- Timer/Counter Interrupt Mask Register – TIMSK
- Timer/Counter Interrupt Flag Register – TIFR
- External Interrupts
- Interrupt Response Time
- MCU Control Register – MCUCR
- Sleep Modes
- Timer/Counters
- 16-bit Timer/Counter1
- Watchdog Timer
- EEPROM Read/Write Access
- Serial Peripheral Interface – SPI
- UART
- Analog Comparator
- Analog-to-Digital Converter
- I/O Ports
- Memory Programming
- Electrical Characteristics
- External Clock Drive Waveforms
- Typical Characteristics
- Register Summary
- Instruction Set Summary
- Ordering Information
- Packaging Information
- Errata for AT90S/LS4433 Rev. Rev. C/D/E/F
- Data Sheet ChangeLog for AT90S/LS4433
- Table of Contents
8
AT90S/LS4433
1042G–AVR–09/02
The I/O memory space contains 64 addresses for CPU peripheral functions such as
Control Registers, Timer/Counters, A/D Converters and other I/O functions. The I/O
memory can be accessed directly, or as the Data Space locations following those of the
Register File, $20 - $5F.
The AVR uses a Harvard architecture concept – with separate memories and buses for
program and data. The Program memory is executed with a two-stage pipeline. While
one instruction is being executed, the next instruction is pre-fetched from the Program
memory. This concept enables instructions to be executed in every clock cycle.
The Program memory is In-System Programmable Flash memory.
With the relative jump and call instructions, the whole 2K word address space is directly
accessed. Most AVR instructions have a single 16-bit word format. Every program
memory address contains a 16- or 32-bit instruction.
During interrupts and subroutine calls, the return address Program Counter (PC) is
stored on the Stack. The Stack is effectively allocated in the general data SRAM and,
consequently, the Stack size is only limited by the total SRAM size and the usage of the
SRAM. All user programs must initialize the SP in the reset routine (before subroutines
or interrupts are executed). The 8-bit Stack Pointer (SP) is read/write accessible in the
I/O space.
The 128 bytes of data SRAM can be easily accessed through the five different address-
ing modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.